STM32_BMS
Interfacing STM32F446ZE with BQ76942 BMS ic over SPI
stm32f446xx.h
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1 
33 #ifndef __STM32F446xx_H
34 #define __STM32F446xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
47 #define __CM4_REV 0x0001U
48 #define __MPU_PRESENT 1U
49 #define __NVIC_PRIO_BITS 4U
50 #define __Vendor_SysTickConfig 0U
51 #define __FPU_PRESENT 1U
65 typedef enum
66 {
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68  NonMaskableInt_IRQn = -14,
69  MemoryManagement_IRQn = -12,
70  BusFault_IRQn = -11,
71  UsageFault_IRQn = -10,
72  SVCall_IRQn = -5,
73  DebugMonitor_IRQn = -4,
74  PendSV_IRQn = -2,
75  SysTick_IRQn = -1,
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
77  WWDG_IRQn = 0,
78  PVD_IRQn = 1,
79  TAMP_STAMP_IRQn = 2,
80  RTC_WKUP_IRQn = 3,
81  FLASH_IRQn = 4,
82  RCC_IRQn = 5,
83  EXTI0_IRQn = 6,
84  EXTI1_IRQn = 7,
85  EXTI2_IRQn = 8,
86  EXTI3_IRQn = 9,
87  EXTI4_IRQn = 10,
88  DMA1_Stream0_IRQn = 11,
89  DMA1_Stream1_IRQn = 12,
90  DMA1_Stream2_IRQn = 13,
91  DMA1_Stream3_IRQn = 14,
92  DMA1_Stream4_IRQn = 15,
93  DMA1_Stream5_IRQn = 16,
94  DMA1_Stream6_IRQn = 17,
95  ADC_IRQn = 18,
96  CAN1_TX_IRQn = 19,
97  CAN1_RX0_IRQn = 20,
98  CAN1_RX1_IRQn = 21,
99  CAN1_SCE_IRQn = 22,
100  EXTI9_5_IRQn = 23,
101  TIM1_BRK_TIM9_IRQn = 24,
102  TIM1_UP_TIM10_IRQn = 25,
103  TIM1_TRG_COM_TIM11_IRQn = 26,
104  TIM1_CC_IRQn = 27,
105  TIM2_IRQn = 28,
106  TIM3_IRQn = 29,
107  TIM4_IRQn = 30,
108  I2C1_EV_IRQn = 31,
109  I2C1_ER_IRQn = 32,
110  I2C2_EV_IRQn = 33,
111  I2C2_ER_IRQn = 34,
112  SPI1_IRQn = 35,
113  SPI2_IRQn = 36,
114  USART1_IRQn = 37,
115  USART2_IRQn = 38,
116  USART3_IRQn = 39,
117  EXTI15_10_IRQn = 40,
118  RTC_Alarm_IRQn = 41,
119  OTG_FS_WKUP_IRQn = 42,
120  TIM8_BRK_TIM12_IRQn = 43,
121  TIM8_UP_TIM13_IRQn = 44,
122  TIM8_TRG_COM_TIM14_IRQn = 45,
123  TIM8_CC_IRQn = 46,
124  DMA1_Stream7_IRQn = 47,
125  FMC_IRQn = 48,
126  SDIO_IRQn = 49,
127  TIM5_IRQn = 50,
128  SPI3_IRQn = 51,
129  UART4_IRQn = 52,
130  UART5_IRQn = 53,
131  TIM6_DAC_IRQn = 54,
132  TIM7_IRQn = 55,
133  DMA2_Stream0_IRQn = 56,
134  DMA2_Stream1_IRQn = 57,
135  DMA2_Stream2_IRQn = 58,
136  DMA2_Stream3_IRQn = 59,
137  DMA2_Stream4_IRQn = 60,
138  CAN2_TX_IRQn = 63,
139  CAN2_RX0_IRQn = 64,
140  CAN2_RX1_IRQn = 65,
141  CAN2_SCE_IRQn = 66,
142  OTG_FS_IRQn = 67,
143  DMA2_Stream5_IRQn = 68,
144  DMA2_Stream6_IRQn = 69,
145  DMA2_Stream7_IRQn = 70,
146  USART6_IRQn = 71,
147  I2C3_EV_IRQn = 72,
148  I2C3_ER_IRQn = 73,
149  OTG_HS_EP1_OUT_IRQn = 74,
150  OTG_HS_EP1_IN_IRQn = 75,
151  OTG_HS_WKUP_IRQn = 76,
152  OTG_HS_IRQn = 77,
153  DCMI_IRQn = 78,
154  FPU_IRQn = 81,
155  SPI4_IRQn = 84,
156  SAI1_IRQn = 87,
157  SAI2_IRQn = 91,
158  QUADSPI_IRQn = 92,
159  CEC_IRQn = 93,
160  SPDIF_RX_IRQn = 94,
161  FMPI2C1_EV_IRQn = 95,
162  FMPI2C1_ER_IRQn = 96
163 } IRQn_Type;
164 
169 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
170 #include "system_stm32f4xx.h"
171 #include <stdint.h>
172 
181 typedef struct
182 {
183  __IO uint32_t SR;
184  __IO uint32_t CR1;
185  __IO uint32_t CR2;
186  __IO uint32_t SMPR1;
187  __IO uint32_t SMPR2;
188  __IO uint32_t JOFR1;
189  __IO uint32_t JOFR2;
190  __IO uint32_t JOFR3;
191  __IO uint32_t JOFR4;
192  __IO uint32_t HTR;
193  __IO uint32_t LTR;
194  __IO uint32_t SQR1;
195  __IO uint32_t SQR2;
196  __IO uint32_t SQR3;
197  __IO uint32_t JSQR;
198  __IO uint32_t JDR1;
199  __IO uint32_t JDR2;
200  __IO uint32_t JDR3;
201  __IO uint32_t JDR4;
202  __IO uint32_t DR;
203 } ADC_TypeDef;
204 
205 typedef struct
206 {
207  __IO uint32_t CSR;
208  __IO uint32_t CCR;
209  __IO uint32_t CDR;
211 } ADC_Common_TypeDef;
212 
213 
218 typedef struct
219 {
220  __IO uint32_t TIR;
221  __IO uint32_t TDTR;
222  __IO uint32_t TDLR;
223  __IO uint32_t TDHR;
224 } CAN_TxMailBox_TypeDef;
225 
230 typedef struct
231 {
232  __IO uint32_t RIR;
233  __IO uint32_t RDTR;
234  __IO uint32_t RDLR;
235  __IO uint32_t RDHR;
236 } CAN_FIFOMailBox_TypeDef;
237 
242 typedef struct
243 {
244  __IO uint32_t FR1;
245  __IO uint32_t FR2;
246 } CAN_FilterRegister_TypeDef;
247 
252 typedef struct
253 {
254  __IO uint32_t MCR;
255  __IO uint32_t MSR;
256  __IO uint32_t TSR;
257  __IO uint32_t RF0R;
258  __IO uint32_t RF1R;
259  __IO uint32_t IER;
260  __IO uint32_t ESR;
261  __IO uint32_t BTR;
262  uint32_t RESERVED0[88];
263  CAN_TxMailBox_TypeDef sTxMailBox[3];
264  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
265  uint32_t RESERVED1[12];
266  __IO uint32_t FMR;
267  __IO uint32_t FM1R;
268  uint32_t RESERVED2;
269  __IO uint32_t FS1R;
270  uint32_t RESERVED3;
271  __IO uint32_t FFA1R;
272  uint32_t RESERVED4;
273  __IO uint32_t FA1R;
274  uint32_t RESERVED5[8];
275  CAN_FilterRegister_TypeDef sFilterRegister[28];
276 } CAN_TypeDef;
277 
278 
283 typedef struct
284 {
285  __IO uint32_t CR;
286  __IO uint32_t CFGR;
287  __IO uint32_t TXDR;
288  __IO uint32_t RXDR;
289  __IO uint32_t ISR;
290  __IO uint32_t IER;
291 }CEC_TypeDef;
296 typedef struct
297 {
298  __IO uint32_t DR;
299  __IO uint8_t IDR;
300  uint8_t RESERVED0;
301  uint16_t RESERVED1;
302  __IO uint32_t CR;
303 } CRC_TypeDef;
304 
309 typedef struct
310 {
311  __IO uint32_t CR;
312  __IO uint32_t SWTRIGR;
313  __IO uint32_t DHR12R1;
314  __IO uint32_t DHR12L1;
315  __IO uint32_t DHR8R1;
316  __IO uint32_t DHR12R2;
317  __IO uint32_t DHR12L2;
318  __IO uint32_t DHR8R2;
319  __IO uint32_t DHR12RD;
320  __IO uint32_t DHR12LD;
321  __IO uint32_t DHR8RD;
322  __IO uint32_t DOR1;
323  __IO uint32_t DOR2;
324  __IO uint32_t SR;
325 } DAC_TypeDef;
326 
331 typedef struct
332 {
333  __IO uint32_t IDCODE;
334  __IO uint32_t CR;
335  __IO uint32_t APB1FZ;
336  __IO uint32_t APB2FZ;
337 }DBGMCU_TypeDef;
338 
343 typedef struct
344 {
345  __IO uint32_t CR;
346  __IO uint32_t SR;
347  __IO uint32_t RISR;
348  __IO uint32_t IER;
349  __IO uint32_t MISR;
350  __IO uint32_t ICR;
351  __IO uint32_t ESCR;
352  __IO uint32_t ESUR;
353  __IO uint32_t CWSTRTR;
354  __IO uint32_t CWSIZER;
355  __IO uint32_t DR;
356 } DCMI_TypeDef;
357 
362 typedef struct
363 {
364  __IO uint32_t CR;
365  __IO uint32_t NDTR;
366  __IO uint32_t PAR;
367  __IO uint32_t M0AR;
368  __IO uint32_t M1AR;
369  __IO uint32_t FCR;
370 } DMA_Stream_TypeDef;
371 
372 typedef struct
373 {
374  __IO uint32_t LISR;
375  __IO uint32_t HISR;
376  __IO uint32_t LIFCR;
377  __IO uint32_t HIFCR;
378 } DMA_TypeDef;
379 
384 typedef struct
385 {
386  __IO uint32_t IMR;
387  __IO uint32_t EMR;
388  __IO uint32_t RTSR;
389  __IO uint32_t FTSR;
390  __IO uint32_t SWIER;
391  __IO uint32_t PR;
392 } EXTI_TypeDef;
393 
398 typedef struct
399 {
400  __IO uint32_t ACR;
401  __IO uint32_t KEYR;
402  __IO uint32_t OPTKEYR;
403  __IO uint32_t SR;
404  __IO uint32_t CR;
405  __IO uint32_t OPTCR;
406  __IO uint32_t OPTCR1;
407 } FLASH_TypeDef;
408 
413 typedef struct
414 {
415  __IO uint32_t BTCR[8];
416 } FMC_Bank1_TypeDef;
417 
422 typedef struct
423 {
424  __IO uint32_t BWTR[7];
425 } FMC_Bank1E_TypeDef;
426 
431 typedef struct
432 {
433  __IO uint32_t PCR;
434  __IO uint32_t SR;
435  __IO uint32_t PMEM;
436  __IO uint32_t PATT;
437  uint32_t RESERVED;
438  __IO uint32_t ECCR;
439 } FMC_Bank3_TypeDef;
440 
445 typedef struct
446 {
447  __IO uint32_t SDCR[2];
448  __IO uint32_t SDTR[2];
449  __IO uint32_t SDCMR;
450  __IO uint32_t SDRTR;
451  __IO uint32_t SDSR;
452 } FMC_Bank5_6_TypeDef;
453 
458 typedef struct
459 {
460  __IO uint32_t MODER;
461  __IO uint32_t OTYPER;
462  __IO uint32_t OSPEEDR;
463  __IO uint32_t PUPDR;
464  __IO uint32_t IDR;
465  __IO uint32_t ODR;
466  __IO uint32_t BSRR;
467  __IO uint32_t LCKR;
468  __IO uint32_t AFR[2];
469 } GPIO_TypeDef;
470 
475 typedef struct
476 {
477  __IO uint32_t MEMRMP;
478  __IO uint32_t PMC;
479  __IO uint32_t EXTICR[4];
480  uint32_t RESERVED[2];
481  __IO uint32_t CMPCR;
482  uint32_t RESERVED1[2];
483  __IO uint32_t CFGR;
484 } SYSCFG_TypeDef;
485 
490 typedef struct
491 {
492  __IO uint32_t CR1;
493  __IO uint32_t CR2;
494  __IO uint32_t OAR1;
495  __IO uint32_t OAR2;
496  __IO uint32_t DR;
497  __IO uint32_t SR1;
498  __IO uint32_t SR2;
499  __IO uint32_t CCR;
500  __IO uint32_t TRISE;
501  __IO uint32_t FLTR;
502 } I2C_TypeDef;
503 
508 typedef struct
509 {
510  __IO uint32_t CR1;
511  __IO uint32_t CR2;
512  __IO uint32_t OAR1;
513  __IO uint32_t OAR2;
514  __IO uint32_t TIMINGR;
515  __IO uint32_t TIMEOUTR;
516  __IO uint32_t ISR;
517  __IO uint32_t ICR;
518  __IO uint32_t PECR;
519  __IO uint32_t RXDR;
520  __IO uint32_t TXDR;
521 } FMPI2C_TypeDef;
522 
527 typedef struct
528 {
529  __IO uint32_t KR;
530  __IO uint32_t PR;
531  __IO uint32_t RLR;
532  __IO uint32_t SR;
533 } IWDG_TypeDef;
534 
535 
540 typedef struct
541 {
542  __IO uint32_t CR;
543  __IO uint32_t CSR;
544 } PWR_TypeDef;
545 
550 typedef struct
551 {
552  __IO uint32_t CR;
553  __IO uint32_t PLLCFGR;
554  __IO uint32_t CFGR;
555  __IO uint32_t CIR;
556  __IO uint32_t AHB1RSTR;
557  __IO uint32_t AHB2RSTR;
558  __IO uint32_t AHB3RSTR;
559  uint32_t RESERVED0;
560  __IO uint32_t APB1RSTR;
561  __IO uint32_t APB2RSTR;
562  uint32_t RESERVED1[2];
563  __IO uint32_t AHB1ENR;
564  __IO uint32_t AHB2ENR;
565  __IO uint32_t AHB3ENR;
566  uint32_t RESERVED2;
567  __IO uint32_t APB1ENR;
568  __IO uint32_t APB2ENR;
569  uint32_t RESERVED3[2];
570  __IO uint32_t AHB1LPENR;
571  __IO uint32_t AHB2LPENR;
572  __IO uint32_t AHB3LPENR;
573  uint32_t RESERVED4;
574  __IO uint32_t APB1LPENR;
575  __IO uint32_t APB2LPENR;
576  uint32_t RESERVED5[2];
577  __IO uint32_t BDCR;
578  __IO uint32_t CSR;
579  uint32_t RESERVED6[2];
580  __IO uint32_t SSCGR;
581  __IO uint32_t PLLI2SCFGR;
582  __IO uint32_t PLLSAICFGR;
583  __IO uint32_t DCKCFGR;
584  __IO uint32_t CKGATENR;
585  __IO uint32_t DCKCFGR2;
586 } RCC_TypeDef;
587 
592 typedef struct
593 {
594  __IO uint32_t TR;
595  __IO uint32_t DR;
596  __IO uint32_t CR;
597  __IO uint32_t ISR;
598  __IO uint32_t PRER;
599  __IO uint32_t WUTR;
600  __IO uint32_t CALIBR;
601  __IO uint32_t ALRMAR;
602  __IO uint32_t ALRMBR;
603  __IO uint32_t WPR;
604  __IO uint32_t SSR;
605  __IO uint32_t SHIFTR;
606  __IO uint32_t TSTR;
607  __IO uint32_t TSDR;
608  __IO uint32_t TSSSR;
609  __IO uint32_t CALR;
610  __IO uint32_t TAFCR;
611  __IO uint32_t ALRMASSR;
612  __IO uint32_t ALRMBSSR;
613  uint32_t RESERVED7;
614  __IO uint32_t BKP0R;
615  __IO uint32_t BKP1R;
616  __IO uint32_t BKP2R;
617  __IO uint32_t BKP3R;
618  __IO uint32_t BKP4R;
619  __IO uint32_t BKP5R;
620  __IO uint32_t BKP6R;
621  __IO uint32_t BKP7R;
622  __IO uint32_t BKP8R;
623  __IO uint32_t BKP9R;
624  __IO uint32_t BKP10R;
625  __IO uint32_t BKP11R;
626  __IO uint32_t BKP12R;
627  __IO uint32_t BKP13R;
628  __IO uint32_t BKP14R;
629  __IO uint32_t BKP15R;
630  __IO uint32_t BKP16R;
631  __IO uint32_t BKP17R;
632  __IO uint32_t BKP18R;
633  __IO uint32_t BKP19R;
634 } RTC_TypeDef;
635 
640 typedef struct
641 {
642  __IO uint32_t GCR;
643 } SAI_TypeDef;
644 
645 typedef struct
646 {
647  __IO uint32_t CR1;
648  __IO uint32_t CR2;
649  __IO uint32_t FRCR;
650  __IO uint32_t SLOTR;
651  __IO uint32_t IMR;
652  __IO uint32_t SR;
653  __IO uint32_t CLRFR;
654  __IO uint32_t DR;
655 } SAI_Block_TypeDef;
656 
661 typedef struct
662 {
663  __IO uint32_t POWER;
664  __IO uint32_t CLKCR;
665  __IO uint32_t ARG;
666  __IO uint32_t CMD;
667  __IO const uint32_t RESPCMD;
668  __IO const uint32_t RESP1;
669  __IO const uint32_t RESP2;
670  __IO const uint32_t RESP3;
671  __IO const uint32_t RESP4;
672  __IO uint32_t DTIMER;
673  __IO uint32_t DLEN;
674  __IO uint32_t DCTRL;
675  __IO const uint32_t DCOUNT;
676  __IO const uint32_t STA;
677  __IO uint32_t ICR;
678  __IO uint32_t MASK;
679  uint32_t RESERVED0[2];
680  __IO const uint32_t FIFOCNT;
681  uint32_t RESERVED1[13];
682  __IO uint32_t FIFO;
683 } SDIO_TypeDef;
684 
689 typedef struct
690 {
691  __IO uint32_t CR1;
692  __IO uint32_t CR2;
693  __IO uint32_t SR;
694  __IO uint32_t DR;
695  __IO uint32_t CRCPR;
696  __IO uint32_t RXCRCR;
697  __IO uint32_t TXCRCR;
698  __IO uint32_t I2SCFGR;
699  __IO uint32_t I2SPR;
700 } SPI_TypeDef;
701 
706 typedef struct
707 {
708  __IO uint32_t CR;
709  __IO uint32_t DCR;
710  __IO uint32_t SR;
711  __IO uint32_t FCR;
712  __IO uint32_t DLR;
713  __IO uint32_t CCR;
714  __IO uint32_t AR;
715  __IO uint32_t ABR;
716  __IO uint32_t DR;
717  __IO uint32_t PSMKR;
718  __IO uint32_t PSMAR;
719  __IO uint32_t PIR;
720  __IO uint32_t LPTR;
721 } QUADSPI_TypeDef;
722 
727 typedef struct
728 {
729  __IO uint32_t CR;
730  __IO uint16_t IMR;
731  uint16_t RESERVED0;
732  __IO uint32_t SR;
733  __IO uint16_t IFCR;
734  uint16_t RESERVED1;
735  __IO uint32_t DR;
736  __IO uint32_t CSR;
737  __IO uint32_t DIR;
738  uint16_t RESERVED2;
739 } SPDIFRX_TypeDef;
740 
745 typedef struct
746 {
747  __IO uint32_t CR1;
748  __IO uint32_t CR2;
749  __IO uint32_t SMCR;
750  __IO uint32_t DIER;
751  __IO uint32_t SR;
752  __IO uint32_t EGR;
753  __IO uint32_t CCMR1;
754  __IO uint32_t CCMR2;
755  __IO uint32_t CCER;
756  __IO uint32_t CNT;
757  __IO uint32_t PSC;
758  __IO uint32_t ARR;
759  __IO uint32_t RCR;
760  __IO uint32_t CCR1;
761  __IO uint32_t CCR2;
762  __IO uint32_t CCR3;
763  __IO uint32_t CCR4;
764  __IO uint32_t BDTR;
765  __IO uint32_t DCR;
766  __IO uint32_t DMAR;
767  __IO uint32_t OR;
768 } TIM_TypeDef;
769 
774 typedef struct
775 {
776  __IO uint32_t SR;
777  __IO uint32_t DR;
778  __IO uint32_t BRR;
779  __IO uint32_t CR1;
780  __IO uint32_t CR2;
781  __IO uint32_t CR3;
782  __IO uint32_t GTPR;
783 } USART_TypeDef;
784 
789 typedef struct
790 {
791  __IO uint32_t CR;
792  __IO uint32_t CFR;
793  __IO uint32_t SR;
794 } WWDG_TypeDef;
798 typedef struct
799 {
800  __IO uint32_t GOTGCTL;
801  __IO uint32_t GOTGINT;
802  __IO uint32_t GAHBCFG;
803  __IO uint32_t GUSBCFG;
804  __IO uint32_t GRSTCTL;
805  __IO uint32_t GINTSTS;
806  __IO uint32_t GINTMSK;
807  __IO uint32_t GRXSTSR;
808  __IO uint32_t GRXSTSP;
809  __IO uint32_t GRXFSIZ;
810  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
811  __IO uint32_t HNPTXSTS;
812  uint32_t Reserved30[2];
813  __IO uint32_t GCCFG;
814  __IO uint32_t CID;
815  uint32_t Reserved5[3];
816  __IO uint32_t GHWCFG3;
817  uint32_t Reserved6;
818  __IO uint32_t GLPMCFG;
819  uint32_t Reserved;
820  __IO uint32_t GDFIFOCFG;
821  uint32_t Reserved43[40];
822  __IO uint32_t HPTXFSIZ;
823  __IO uint32_t DIEPTXF[0x0F];
824 } USB_OTG_GlobalTypeDef;
825 
829 typedef struct
830 {
831  __IO uint32_t DCFG;
832  __IO uint32_t DCTL;
833  __IO uint32_t DSTS;
834  uint32_t Reserved0C;
835  __IO uint32_t DIEPMSK;
836  __IO uint32_t DOEPMSK;
837  __IO uint32_t DAINT;
838  __IO uint32_t DAINTMSK;
839  uint32_t Reserved20;
840  uint32_t Reserved9;
841  __IO uint32_t DVBUSDIS;
842  __IO uint32_t DVBUSPULSE;
843  __IO uint32_t DTHRCTL;
844  __IO uint32_t DIEPEMPMSK;
845  __IO uint32_t DEACHINT;
846  __IO uint32_t DEACHMSK;
847  uint32_t Reserved40;
848  __IO uint32_t DINEP1MSK;
849  uint32_t Reserved44[15];
850  __IO uint32_t DOUTEP1MSK;
851 } USB_OTG_DeviceTypeDef;
852 
856 typedef struct
857 {
858  __IO uint32_t DIEPCTL;
859  uint32_t Reserved04;
860  __IO uint32_t DIEPINT;
861  uint32_t Reserved0C;
862  __IO uint32_t DIEPTSIZ;
863  __IO uint32_t DIEPDMA;
864  __IO uint32_t DTXFSTS;
865  uint32_t Reserved18;
866 } USB_OTG_INEndpointTypeDef;
867 
871 typedef struct
872 {
873  __IO uint32_t DOEPCTL;
874  uint32_t Reserved04;
875  __IO uint32_t DOEPINT;
876  uint32_t Reserved0C;
877  __IO uint32_t DOEPTSIZ;
878  __IO uint32_t DOEPDMA;
879  uint32_t Reserved18[2];
880 } USB_OTG_OUTEndpointTypeDef;
881 
885 typedef struct
886 {
887  __IO uint32_t HCFG;
888  __IO uint32_t HFIR;
889  __IO uint32_t HFNUM;
890  uint32_t Reserved40C;
891  __IO uint32_t HPTXSTS;
892  __IO uint32_t HAINT;
893  __IO uint32_t HAINTMSK;
894 } USB_OTG_HostTypeDef;
895 
899 typedef struct
900 {
901  __IO uint32_t HCCHAR;
902  __IO uint32_t HCSPLT;
903  __IO uint32_t HCINT;
904  __IO uint32_t HCINTMSK;
905  __IO uint32_t HCTSIZ;
906  __IO uint32_t HCDMA;
907  uint32_t Reserved[2];
908 } USB_OTG_HostChannelTypeDef;
909 
917 #define FLASH_BASE 0x08000000UL
918 #define SRAM1_BASE 0x20000000UL
919 #define SRAM2_BASE 0x2001C000UL
920 #define PERIPH_BASE 0x40000000UL
921 #define BKPSRAM_BASE 0x40024000UL
922 #define FMC_R_BASE 0xA0000000UL
923 #define QSPI_R_BASE 0xA0001000UL
924 #define SRAM1_BB_BASE 0x22000000UL
925 #define SRAM2_BB_BASE 0x22380000UL
926 #define PERIPH_BB_BASE 0x42000000UL
927 #define BKPSRAM_BB_BASE 0x42480000UL
928 #define FLASH_END 0x0807FFFFUL
929 #define FLASH_OTP_BASE 0x1FFF7800UL
930 #define FLASH_OTP_END 0x1FFF7A0FUL
932 /* Legacy defines */
933 #define SRAM_BASE SRAM1_BASE
934 #define SRAM_BB_BASE SRAM1_BB_BASE
935 
937 #define APB1PERIPH_BASE PERIPH_BASE
938 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
939 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
940 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
941 
943 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
944 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
945 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
946 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
947 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
948 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
949 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
950 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
951 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
952 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
953 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
954 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
955 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
956 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
957 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)
958 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
959 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
960 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
961 #define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
962 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
963 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
964 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
965 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL)
966 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
967 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
968 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)
969 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
970 #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
971 
973 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
974 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
975 #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
976 #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
977 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
978 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
979 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
980 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
981 /* Legacy define */
982 #define ADC_BASE ADC123_COMMON_BASE
983 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
984 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
985 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
986 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
987 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
988 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
989 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
990 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
991 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
992 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
993 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
994 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
995 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
996 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
997 
999 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1000 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1001 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1002 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1003 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1004 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1005 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1006 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1007 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1008 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1009 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1010 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1011 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1012 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1013 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1014 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1015 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1016 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1017 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1018 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1019 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1020 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1021 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1022 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1023 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1024 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1025 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1026 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1027 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1028 
1030 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1031 
1033 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1034 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1035 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1036 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1037 
1038 
1040 #define DBGMCU_BASE 0xE0042000UL
1042 #define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1043 #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1044 
1045 #define USB_OTG_GLOBAL_BASE 0x000UL
1046 #define USB_OTG_DEVICE_BASE 0x800UL
1047 #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1048 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1049 #define USB_OTG_EP_REG_SIZE 0x20UL
1050 #define USB_OTG_HOST_BASE 0x400UL
1051 #define USB_OTG_HOST_PORT_BASE 0x440UL
1052 #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1053 #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1054 #define USB_OTG_PCGCCTL_BASE 0xE00UL
1055 #define USB_OTG_FIFO_BASE 0x1000UL
1056 #define USB_OTG_FIFO_SIZE 0x1000UL
1057 
1058 #define UID_BASE 0x1FFF7A10UL
1059 #define FLASHSIZE_BASE 0x1FFF7A22UL
1060 #define PACKAGE_BASE 0x1FFF7BF0UL
1068 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1069 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1070 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1071 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1072 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1073 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1074 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1075 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1076 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1077 #define RTC ((RTC_TypeDef *) RTC_BASE)
1078 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1079 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1080 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1081 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1082 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1083 #define USART2 ((USART_TypeDef *) USART2_BASE)
1084 #define USART3 ((USART_TypeDef *) USART3_BASE)
1085 #define UART4 ((USART_TypeDef *) UART4_BASE)
1086 #define UART5 ((USART_TypeDef *) UART5_BASE)
1087 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1088 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1089 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1090 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1091 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1092 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1093 #define CEC ((CEC_TypeDef *) CEC_BASE)
1094 #define PWR ((PWR_TypeDef *) PWR_BASE)
1095 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1096 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1097 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1098 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1099 #define USART1 ((USART_TypeDef *) USART1_BASE)
1100 #define USART6 ((USART_TypeDef *) USART6_BASE)
1101 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1102 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1103 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1104 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1105 /* Legacy define */
1106 #define ADC ADC123_COMMON
1107 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1108 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1109 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1110 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1111 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1112 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1113 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1114 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1115 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1116 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1117 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1118 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1119 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1120 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1121 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1122 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1123 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1124 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1125 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1126 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1127 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1128 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1129 #define CRC ((CRC_TypeDef *) CRC_BASE)
1130 #define RCC ((RCC_TypeDef *) RCC_BASE)
1131 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1132 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1133 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1134 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1135 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1136 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1137 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1138 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1139 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1140 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1141 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1142 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1143 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1144 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1145 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1146 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1147 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1148 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1149 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1150 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1151 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1152 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1153 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1154 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1155 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1156 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1157 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1158 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1159 
1171 #define LSI_STARTUP_TIME 40U
1180 /******************************************************************************/
1181 /* Peripheral Registers_Bits_Definition */
1182 /******************************************************************************/
1183 
1184 /******************************************************************************/
1185 /* */
1186 /* Analog to Digital Converter */
1187 /* */
1188 /******************************************************************************/
1189 /*
1190  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1191  */
1192 #define ADC_MULTIMODE_SUPPORT
1194 /******************** Bit definition for ADC_SR register ********************/
1195 #define ADC_SR_AWD_Pos (0U)
1196 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1197 #define ADC_SR_AWD ADC_SR_AWD_Msk
1198 #define ADC_SR_EOC_Pos (1U)
1199 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1200 #define ADC_SR_EOC ADC_SR_EOC_Msk
1201 #define ADC_SR_JEOC_Pos (2U)
1202 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1203 #define ADC_SR_JEOC ADC_SR_JEOC_Msk
1204 #define ADC_SR_JSTRT_Pos (3U)
1205 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1206 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1207 #define ADC_SR_STRT_Pos (4U)
1208 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1209 #define ADC_SR_STRT ADC_SR_STRT_Msk
1210 #define ADC_SR_OVR_Pos (5U)
1211 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1212 #define ADC_SR_OVR ADC_SR_OVR_Msk
1214 /******************* Bit definition for ADC_CR1 register ********************/
1215 #define ADC_CR1_AWDCH_Pos (0U)
1216 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1217 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1218 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1219 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1220 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1221 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1222 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1223 #define ADC_CR1_EOCIE_Pos (5U)
1224 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1225 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1226 #define ADC_CR1_AWDIE_Pos (6U)
1227 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1228 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1229 #define ADC_CR1_JEOCIE_Pos (7U)
1230 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1231 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1232 #define ADC_CR1_SCAN_Pos (8U)
1233 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1234 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1235 #define ADC_CR1_AWDSGL_Pos (9U)
1236 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1237 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1238 #define ADC_CR1_JAUTO_Pos (10U)
1239 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1240 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1241 #define ADC_CR1_DISCEN_Pos (11U)
1242 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1243 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1244 #define ADC_CR1_JDISCEN_Pos (12U)
1245 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1246 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1247 #define ADC_CR1_DISCNUM_Pos (13U)
1248 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1249 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1250 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1251 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1252 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1253 #define ADC_CR1_JAWDEN_Pos (22U)
1254 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1255 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1256 #define ADC_CR1_AWDEN_Pos (23U)
1257 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1258 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1259 #define ADC_CR1_RES_Pos (24U)
1260 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1261 #define ADC_CR1_RES ADC_CR1_RES_Msk
1262 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1263 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1264 #define ADC_CR1_OVRIE_Pos (26U)
1265 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1266 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1268 /******************* Bit definition for ADC_CR2 register ********************/
1269 #define ADC_CR2_ADON_Pos (0U)
1270 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1271 #define ADC_CR2_ADON ADC_CR2_ADON_Msk
1272 #define ADC_CR2_CONT_Pos (1U)
1273 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1274 #define ADC_CR2_CONT ADC_CR2_CONT_Msk
1275 #define ADC_CR2_DMA_Pos (8U)
1276 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1277 #define ADC_CR2_DMA ADC_CR2_DMA_Msk
1278 #define ADC_CR2_DDS_Pos (9U)
1279 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1280 #define ADC_CR2_DDS ADC_CR2_DDS_Msk
1281 #define ADC_CR2_EOCS_Pos (10U)
1282 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1283 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1284 #define ADC_CR2_ALIGN_Pos (11U)
1285 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1286 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1287 #define ADC_CR2_JEXTSEL_Pos (16U)
1288 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1289 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1290 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1291 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1292 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1293 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1294 #define ADC_CR2_JEXTEN_Pos (20U)
1295 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1296 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1297 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1298 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1299 #define ADC_CR2_JSWSTART_Pos (22U)
1300 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1301 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1302 #define ADC_CR2_EXTSEL_Pos (24U)
1303 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1304 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1305 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1306 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1307 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1308 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1309 #define ADC_CR2_EXTEN_Pos (28U)
1310 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1311 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1312 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1313 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1314 #define ADC_CR2_SWSTART_Pos (30U)
1315 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1316 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1318 /****************** Bit definition for ADC_SMPR1 register *******************/
1319 #define ADC_SMPR1_SMP10_Pos (0U)
1320 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1321 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1322 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1323 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1324 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1325 #define ADC_SMPR1_SMP11_Pos (3U)
1326 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1327 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1328 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1329 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1330 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1331 #define ADC_SMPR1_SMP12_Pos (6U)
1332 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1333 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1334 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1335 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1336 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1337 #define ADC_SMPR1_SMP13_Pos (9U)
1338 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1339 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1340 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1341 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1342 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1343 #define ADC_SMPR1_SMP14_Pos (12U)
1344 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1345 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1346 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1347 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1348 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1349 #define ADC_SMPR1_SMP15_Pos (15U)
1350 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1351 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1352 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1353 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1354 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1355 #define ADC_SMPR1_SMP16_Pos (18U)
1356 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1357 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1358 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1359 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1360 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1361 #define ADC_SMPR1_SMP17_Pos (21U)
1362 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1363 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1364 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1365 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1366 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1367 #define ADC_SMPR1_SMP18_Pos (24U)
1368 #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1369 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1370 #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1371 #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1372 #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1374 /****************** Bit definition for ADC_SMPR2 register *******************/
1375 #define ADC_SMPR2_SMP0_Pos (0U)
1376 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1377 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1378 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1379 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1380 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1381 #define ADC_SMPR2_SMP1_Pos (3U)
1382 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1383 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1384 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1385 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1386 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1387 #define ADC_SMPR2_SMP2_Pos (6U)
1388 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1389 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1390 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1391 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1392 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1393 #define ADC_SMPR2_SMP3_Pos (9U)
1394 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1395 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1396 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1397 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1398 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1399 #define ADC_SMPR2_SMP4_Pos (12U)
1400 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1401 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1402 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1403 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1404 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1405 #define ADC_SMPR2_SMP5_Pos (15U)
1406 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1407 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1408 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1409 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1410 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1411 #define ADC_SMPR2_SMP6_Pos (18U)
1412 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1413 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1414 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1415 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1416 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1417 #define ADC_SMPR2_SMP7_Pos (21U)
1418 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1419 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1420 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1421 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1422 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1423 #define ADC_SMPR2_SMP8_Pos (24U)
1424 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1425 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1426 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1427 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1428 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1429 #define ADC_SMPR2_SMP9_Pos (27U)
1430 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1431 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1432 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1433 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1434 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1436 /****************** Bit definition for ADC_JOFR1 register *******************/
1437 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1438 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1439 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1441 /****************** Bit definition for ADC_JOFR2 register *******************/
1442 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1443 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1444 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1446 /****************** Bit definition for ADC_JOFR3 register *******************/
1447 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1448 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1449 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1451 /****************** Bit definition for ADC_JOFR4 register *******************/
1452 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1453 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1454 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1456 /******************* Bit definition for ADC_HTR register ********************/
1457 #define ADC_HTR_HT_Pos (0U)
1458 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1459 #define ADC_HTR_HT ADC_HTR_HT_Msk
1461 /******************* Bit definition for ADC_LTR register ********************/
1462 #define ADC_LTR_LT_Pos (0U)
1463 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1464 #define ADC_LTR_LT ADC_LTR_LT_Msk
1466 /******************* Bit definition for ADC_SQR1 register *******************/
1467 #define ADC_SQR1_SQ13_Pos (0U)
1468 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1469 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1470 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1471 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1472 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1473 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1474 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1475 #define ADC_SQR1_SQ14_Pos (5U)
1476 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1477 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1478 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1479 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1480 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1481 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1482 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1483 #define ADC_SQR1_SQ15_Pos (10U)
1484 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1485 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1486 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1487 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1488 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1489 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1490 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1491 #define ADC_SQR1_SQ16_Pos (15U)
1492 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1493 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1494 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1495 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1496 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1497 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1498 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1499 #define ADC_SQR1_L_Pos (20U)
1500 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1501 #define ADC_SQR1_L ADC_SQR1_L_Msk
1502 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1503 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1504 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1505 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1507 /******************* Bit definition for ADC_SQR2 register *******************/
1508 #define ADC_SQR2_SQ7_Pos (0U)
1509 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1510 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1511 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1512 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1513 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1514 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1515 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1516 #define ADC_SQR2_SQ8_Pos (5U)
1517 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1518 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1519 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1520 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1521 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1522 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1523 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1524 #define ADC_SQR2_SQ9_Pos (10U)
1525 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1526 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1527 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1528 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1529 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1530 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1531 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1532 #define ADC_SQR2_SQ10_Pos (15U)
1533 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1534 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1535 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1536 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1537 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1538 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1539 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1540 #define ADC_SQR2_SQ11_Pos (20U)
1541 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1542 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1543 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1544 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1545 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1546 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1547 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1548 #define ADC_SQR2_SQ12_Pos (25U)
1549 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1550 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1551 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1552 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1553 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1554 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1555 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1557 /******************* Bit definition for ADC_SQR3 register *******************/
1558 #define ADC_SQR3_SQ1_Pos (0U)
1559 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1560 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1561 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1562 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1563 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1564 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1565 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1566 #define ADC_SQR3_SQ2_Pos (5U)
1567 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1568 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1569 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1570 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1571 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1572 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1573 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1574 #define ADC_SQR3_SQ3_Pos (10U)
1575 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1576 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1577 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1578 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1579 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1580 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1581 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1582 #define ADC_SQR3_SQ4_Pos (15U)
1583 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1584 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1585 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1586 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1587 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1588 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1589 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1590 #define ADC_SQR3_SQ5_Pos (20U)
1591 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1592 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1593 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1594 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1595 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1596 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1597 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1598 #define ADC_SQR3_SQ6_Pos (25U)
1599 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1600 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1601 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1602 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1603 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1604 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1605 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1607 /******************* Bit definition for ADC_JSQR register *******************/
1608 #define ADC_JSQR_JSQ1_Pos (0U)
1609 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1610 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1611 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1612 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1613 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1614 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1615 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1616 #define ADC_JSQR_JSQ2_Pos (5U)
1617 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1618 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1619 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1620 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1621 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1622 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1623 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1624 #define ADC_JSQR_JSQ3_Pos (10U)
1625 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1626 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1627 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1628 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1629 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1630 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1631 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1632 #define ADC_JSQR_JSQ4_Pos (15U)
1633 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1634 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1635 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1636 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1637 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1638 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1639 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1640 #define ADC_JSQR_JL_Pos (20U)
1641 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1642 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
1643 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1644 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1646 /******************* Bit definition for ADC_JDR1 register *******************/
1647 #define ADC_JDR1_JDATA_Pos (0U)
1648 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1649 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1651 /******************* Bit definition for ADC_JDR2 register *******************/
1652 #define ADC_JDR2_JDATA_Pos (0U)
1653 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1654 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1656 /******************* Bit definition for ADC_JDR3 register *******************/
1657 #define ADC_JDR3_JDATA_Pos (0U)
1658 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1659 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1661 /******************* Bit definition for ADC_JDR4 register *******************/
1662 #define ADC_JDR4_JDATA_Pos (0U)
1663 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1664 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1666 /******************** Bit definition for ADC_DR register ********************/
1667 #define ADC_DR_DATA_Pos (0U)
1668 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1669 #define ADC_DR_DATA ADC_DR_DATA_Msk
1670 #define ADC_DR_ADC2DATA_Pos (16U)
1671 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1672 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1674 /******************* Bit definition for ADC_CSR register ********************/
1675 #define ADC_CSR_AWD1_Pos (0U)
1676 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1677 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1678 #define ADC_CSR_EOC1_Pos (1U)
1679 #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1680 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1681 #define ADC_CSR_JEOC1_Pos (2U)
1682 #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1683 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1684 #define ADC_CSR_JSTRT1_Pos (3U)
1685 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1686 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1687 #define ADC_CSR_STRT1_Pos (4U)
1688 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1689 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1690 #define ADC_CSR_OVR1_Pos (5U)
1691 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1692 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1693 #define ADC_CSR_AWD2_Pos (8U)
1694 #define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1695 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1696 #define ADC_CSR_EOC2_Pos (9U)
1697 #define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1698 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1699 #define ADC_CSR_JEOC2_Pos (10U)
1700 #define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1701 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1702 #define ADC_CSR_JSTRT2_Pos (11U)
1703 #define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1704 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1705 #define ADC_CSR_STRT2_Pos (12U)
1706 #define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1707 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1708 #define ADC_CSR_OVR2_Pos (13U)
1709 #define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1710 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1711 #define ADC_CSR_AWD3_Pos (16U)
1712 #define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1713 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1714 #define ADC_CSR_EOC3_Pos (17U)
1715 #define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1716 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1717 #define ADC_CSR_JEOC3_Pos (18U)
1718 #define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1719 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1720 #define ADC_CSR_JSTRT3_Pos (19U)
1721 #define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1722 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1723 #define ADC_CSR_STRT3_Pos (20U)
1724 #define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1725 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1726 #define ADC_CSR_OVR3_Pos (21U)
1727 #define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1728 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1730 /* Legacy defines */
1731 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1732 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1733 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1734 
1735 /******************* Bit definition for ADC_CCR register ********************/
1736 #define ADC_CCR_MULTI_Pos (0U)
1737 #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1738 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1739 #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1740 #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1741 #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1742 #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1743 #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1744 #define ADC_CCR_DELAY_Pos (8U)
1745 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1746 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1747 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1748 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1749 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1750 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1751 #define ADC_CCR_DDS_Pos (13U)
1752 #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1753 #define ADC_CCR_DDS ADC_CCR_DDS_Msk
1754 #define ADC_CCR_DMA_Pos (14U)
1755 #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1756 #define ADC_CCR_DMA ADC_CCR_DMA_Msk
1757 #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1758 #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1759 #define ADC_CCR_ADCPRE_Pos (16U)
1760 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1761 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1762 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1763 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1764 #define ADC_CCR_VBATE_Pos (22U)
1765 #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1766 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1767 #define ADC_CCR_TSVREFE_Pos (23U)
1768 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1769 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1771 /******************* Bit definition for ADC_CDR register ********************/
1772 #define ADC_CDR_DATA1_Pos (0U)
1773 #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1774 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1775 #define ADC_CDR_DATA2_Pos (16U)
1776 #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1777 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1779 /* Legacy defines */
1780 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1781 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1782 
1783 /******************************************************************************/
1784 /* */
1785 /* Controller Area Network */
1786 /* */
1787 /******************************************************************************/
1789 /******************* Bit definition for CAN_MCR register ********************/
1790 #define CAN_MCR_INRQ_Pos (0U)
1791 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1792 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1793 #define CAN_MCR_SLEEP_Pos (1U)
1794 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1795 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1796 #define CAN_MCR_TXFP_Pos (2U)
1797 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1798 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1799 #define CAN_MCR_RFLM_Pos (3U)
1800 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1801 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1802 #define CAN_MCR_NART_Pos (4U)
1803 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1804 #define CAN_MCR_NART CAN_MCR_NART_Msk
1805 #define CAN_MCR_AWUM_Pos (5U)
1806 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1807 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1808 #define CAN_MCR_ABOM_Pos (6U)
1809 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1810 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1811 #define CAN_MCR_TTCM_Pos (7U)
1812 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1813 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1814 #define CAN_MCR_RESET_Pos (15U)
1815 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1816 #define CAN_MCR_RESET CAN_MCR_RESET_Msk
1817 #define CAN_MCR_DBF_Pos (16U)
1818 #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1819 #define CAN_MCR_DBF CAN_MCR_DBF_Msk
1820 /******************* Bit definition for CAN_MSR register ********************/
1821 #define CAN_MSR_INAK_Pos (0U)
1822 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1823 #define CAN_MSR_INAK CAN_MSR_INAK_Msk
1824 #define CAN_MSR_SLAK_Pos (1U)
1825 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1826 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1827 #define CAN_MSR_ERRI_Pos (2U)
1828 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1829 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1830 #define CAN_MSR_WKUI_Pos (3U)
1831 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1832 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1833 #define CAN_MSR_SLAKI_Pos (4U)
1834 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1835 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1836 #define CAN_MSR_TXM_Pos (8U)
1837 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1838 #define CAN_MSR_TXM CAN_MSR_TXM_Msk
1839 #define CAN_MSR_RXM_Pos (9U)
1840 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1841 #define CAN_MSR_RXM CAN_MSR_RXM_Msk
1842 #define CAN_MSR_SAMP_Pos (10U)
1843 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1844 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1845 #define CAN_MSR_RX_Pos (11U)
1846 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1847 #define CAN_MSR_RX CAN_MSR_RX_Msk
1849 /******************* Bit definition for CAN_TSR register ********************/
1850 #define CAN_TSR_RQCP0_Pos (0U)
1851 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1852 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1853 #define CAN_TSR_TXOK0_Pos (1U)
1854 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1855 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1856 #define CAN_TSR_ALST0_Pos (2U)
1857 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1858 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1859 #define CAN_TSR_TERR0_Pos (3U)
1860 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1861 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1862 #define CAN_TSR_ABRQ0_Pos (7U)
1863 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1864 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1865 #define CAN_TSR_RQCP1_Pos (8U)
1866 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1867 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1868 #define CAN_TSR_TXOK1_Pos (9U)
1869 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1870 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1871 #define CAN_TSR_ALST1_Pos (10U)
1872 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1873 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1874 #define CAN_TSR_TERR1_Pos (11U)
1875 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1876 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1877 #define CAN_TSR_ABRQ1_Pos (15U)
1878 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1879 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1880 #define CAN_TSR_RQCP2_Pos (16U)
1881 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1882 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1883 #define CAN_TSR_TXOK2_Pos (17U)
1884 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1885 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1886 #define CAN_TSR_ALST2_Pos (18U)
1887 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1888 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1889 #define CAN_TSR_TERR2_Pos (19U)
1890 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1891 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1892 #define CAN_TSR_ABRQ2_Pos (23U)
1893 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1894 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1895 #define CAN_TSR_CODE_Pos (24U)
1896 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1897 #define CAN_TSR_CODE CAN_TSR_CODE_Msk
1899 #define CAN_TSR_TME_Pos (26U)
1900 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1901 #define CAN_TSR_TME CAN_TSR_TME_Msk
1902 #define CAN_TSR_TME0_Pos (26U)
1903 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1904 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1905 #define CAN_TSR_TME1_Pos (27U)
1906 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1907 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1908 #define CAN_TSR_TME2_Pos (28U)
1909 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1910 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1912 #define CAN_TSR_LOW_Pos (29U)
1913 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1914 #define CAN_TSR_LOW CAN_TSR_LOW_Msk
1915 #define CAN_TSR_LOW0_Pos (29U)
1916 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1917 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1918 #define CAN_TSR_LOW1_Pos (30U)
1919 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1920 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1921 #define CAN_TSR_LOW2_Pos (31U)
1922 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1923 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1925 /******************* Bit definition for CAN_RF0R register *******************/
1926 #define CAN_RF0R_FMP0_Pos (0U)
1927 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1928 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1929 #define CAN_RF0R_FULL0_Pos (3U)
1930 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1931 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1932 #define CAN_RF0R_FOVR0_Pos (4U)
1933 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1934 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1935 #define CAN_RF0R_RFOM0_Pos (5U)
1936 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1937 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1939 /******************* Bit definition for CAN_RF1R register *******************/
1940 #define CAN_RF1R_FMP1_Pos (0U)
1941 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1942 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1943 #define CAN_RF1R_FULL1_Pos (3U)
1944 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1945 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1946 #define CAN_RF1R_FOVR1_Pos (4U)
1947 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1948 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1949 #define CAN_RF1R_RFOM1_Pos (5U)
1950 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1951 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1953 /******************** Bit definition for CAN_IER register *******************/
1954 #define CAN_IER_TMEIE_Pos (0U)
1955 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1956 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1957 #define CAN_IER_FMPIE0_Pos (1U)
1958 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1959 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1960 #define CAN_IER_FFIE0_Pos (2U)
1961 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1962 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1963 #define CAN_IER_FOVIE0_Pos (3U)
1964 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1965 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1966 #define CAN_IER_FMPIE1_Pos (4U)
1967 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1968 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1969 #define CAN_IER_FFIE1_Pos (5U)
1970 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1971 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1972 #define CAN_IER_FOVIE1_Pos (6U)
1973 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1974 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1975 #define CAN_IER_EWGIE_Pos (8U)
1976 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1977 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1978 #define CAN_IER_EPVIE_Pos (9U)
1979 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1980 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1981 #define CAN_IER_BOFIE_Pos (10U)
1982 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1983 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1984 #define CAN_IER_LECIE_Pos (11U)
1985 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1986 #define CAN_IER_LECIE CAN_IER_LECIE_Msk
1987 #define CAN_IER_ERRIE_Pos (15U)
1988 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1989 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1990 #define CAN_IER_WKUIE_Pos (16U)
1991 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1992 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1993 #define CAN_IER_SLKIE_Pos (17U)
1994 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1995 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1996 #define CAN_IER_EWGIE_Pos (8U)
1997 
1998 /******************** Bit definition for CAN_ESR register *******************/
1999 #define CAN_ESR_EWGF_Pos (0U)
2000 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2001 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2002 #define CAN_ESR_EPVF_Pos (1U)
2003 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2004 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2005 #define CAN_ESR_BOFF_Pos (2U)
2006 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2007 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2009 #define CAN_ESR_LEC_Pos (4U)
2010 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2011 #define CAN_ESR_LEC CAN_ESR_LEC_Msk
2012 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2013 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2014 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2016 #define CAN_ESR_TEC_Pos (16U)
2017 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2018 #define CAN_ESR_TEC CAN_ESR_TEC_Msk
2019 #define CAN_ESR_REC_Pos (24U)
2020 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2021 #define CAN_ESR_REC CAN_ESR_REC_Msk
2023 /******************* Bit definition for CAN_BTR register ********************/
2024 #define CAN_BTR_BRP_Pos (0U)
2025 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2026 #define CAN_BTR_BRP CAN_BTR_BRP_Msk
2027 #define CAN_BTR_TS1_Pos (16U)
2028 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2029 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2030 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2031 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2032 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2033 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2034 #define CAN_BTR_TS2_Pos (20U)
2035 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2036 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2037 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2038 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2039 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2040 #define CAN_BTR_SJW_Pos (24U)
2041 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2042 #define CAN_BTR_SJW CAN_BTR_SJW_Msk
2043 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2044 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2045 #define CAN_BTR_LBKM_Pos (30U)
2046 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2047 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2048 #define CAN_BTR_SILM_Pos (31U)
2049 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2050 #define CAN_BTR_SILM CAN_BTR_SILM_Msk
2054 /****************** Bit definition for CAN_TI0R register ********************/
2055 #define CAN_TI0R_TXRQ_Pos (0U)
2056 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2057 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2058 #define CAN_TI0R_RTR_Pos (1U)
2059 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2060 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2061 #define CAN_TI0R_IDE_Pos (2U)
2062 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2063 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2064 #define CAN_TI0R_EXID_Pos (3U)
2065 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2066 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2067 #define CAN_TI0R_STID_Pos (21U)
2068 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2069 #define CAN_TI0R_STID CAN_TI0R_STID_Msk
2071 /****************** Bit definition for CAN_TDT0R register *******************/
2072 #define CAN_TDT0R_DLC_Pos (0U)
2073 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2074 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2075 #define CAN_TDT0R_TGT_Pos (8U)
2076 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2077 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2078 #define CAN_TDT0R_TIME_Pos (16U)
2079 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2080 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2082 /****************** Bit definition for CAN_TDL0R register *******************/
2083 #define CAN_TDL0R_DATA0_Pos (0U)
2084 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2085 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2086 #define CAN_TDL0R_DATA1_Pos (8U)
2087 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2088 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2089 #define CAN_TDL0R_DATA2_Pos (16U)
2090 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2091 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2092 #define CAN_TDL0R_DATA3_Pos (24U)
2093 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2094 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2096 /****************** Bit definition for CAN_TDH0R register *******************/
2097 #define CAN_TDH0R_DATA4_Pos (0U)
2098 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2099 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2100 #define CAN_TDH0R_DATA5_Pos (8U)
2101 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2102 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2103 #define CAN_TDH0R_DATA6_Pos (16U)
2104 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2105 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2106 #define CAN_TDH0R_DATA7_Pos (24U)
2107 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2108 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2110 /******************* Bit definition for CAN_TI1R register *******************/
2111 #define CAN_TI1R_TXRQ_Pos (0U)
2112 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2113 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2114 #define CAN_TI1R_RTR_Pos (1U)
2115 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2116 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2117 #define CAN_TI1R_IDE_Pos (2U)
2118 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2119 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2120 #define CAN_TI1R_EXID_Pos (3U)
2121 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2122 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2123 #define CAN_TI1R_STID_Pos (21U)
2124 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2125 #define CAN_TI1R_STID CAN_TI1R_STID_Msk
2127 /******************* Bit definition for CAN_TDT1R register ******************/
2128 #define CAN_TDT1R_DLC_Pos (0U)
2129 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2130 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2131 #define CAN_TDT1R_TGT_Pos (8U)
2132 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2133 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2134 #define CAN_TDT1R_TIME_Pos (16U)
2135 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2136 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2138 /******************* Bit definition for CAN_TDL1R register ******************/
2139 #define CAN_TDL1R_DATA0_Pos (0U)
2140 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2141 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2142 #define CAN_TDL1R_DATA1_Pos (8U)
2143 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2144 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2145 #define CAN_TDL1R_DATA2_Pos (16U)
2146 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2147 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2148 #define CAN_TDL1R_DATA3_Pos (24U)
2149 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2150 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2152 /******************* Bit definition for CAN_TDH1R register ******************/
2153 #define CAN_TDH1R_DATA4_Pos (0U)
2154 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2155 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2156 #define CAN_TDH1R_DATA5_Pos (8U)
2157 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2158 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2159 #define CAN_TDH1R_DATA6_Pos (16U)
2160 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2161 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2162 #define CAN_TDH1R_DATA7_Pos (24U)
2163 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2164 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2166 /******************* Bit definition for CAN_TI2R register *******************/
2167 #define CAN_TI2R_TXRQ_Pos (0U)
2168 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2169 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2170 #define CAN_TI2R_RTR_Pos (1U)
2171 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2172 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2173 #define CAN_TI2R_IDE_Pos (2U)
2174 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2175 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2176 #define CAN_TI2R_EXID_Pos (3U)
2177 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2178 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2179 #define CAN_TI2R_STID_Pos (21U)
2180 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2181 #define CAN_TI2R_STID CAN_TI2R_STID_Msk
2183 /******************* Bit definition for CAN_TDT2R register ******************/
2184 #define CAN_TDT2R_DLC_Pos (0U)
2185 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2186 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2187 #define CAN_TDT2R_TGT_Pos (8U)
2188 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2189 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2190 #define CAN_TDT2R_TIME_Pos (16U)
2191 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2192 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2194 /******************* Bit definition for CAN_TDL2R register ******************/
2195 #define CAN_TDL2R_DATA0_Pos (0U)
2196 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2197 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2198 #define CAN_TDL2R_DATA1_Pos (8U)
2199 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2200 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2201 #define CAN_TDL2R_DATA2_Pos (16U)
2202 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2203 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2204 #define CAN_TDL2R_DATA3_Pos (24U)
2205 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2206 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2208 /******************* Bit definition for CAN_TDH2R register ******************/
2209 #define CAN_TDH2R_DATA4_Pos (0U)
2210 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2211 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2212 #define CAN_TDH2R_DATA5_Pos (8U)
2213 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2214 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2215 #define CAN_TDH2R_DATA6_Pos (16U)
2216 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2217 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2218 #define CAN_TDH2R_DATA7_Pos (24U)
2219 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2220 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2222 /******************* Bit definition for CAN_RI0R register *******************/
2223 #define CAN_RI0R_RTR_Pos (1U)
2224 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2225 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2226 #define CAN_RI0R_IDE_Pos (2U)
2227 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2228 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2229 #define CAN_RI0R_EXID_Pos (3U)
2230 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2231 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2232 #define CAN_RI0R_STID_Pos (21U)
2233 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2234 #define CAN_RI0R_STID CAN_RI0R_STID_Msk
2236 /******************* Bit definition for CAN_RDT0R register ******************/
2237 #define CAN_RDT0R_DLC_Pos (0U)
2238 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2239 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2240 #define CAN_RDT0R_FMI_Pos (8U)
2241 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2242 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2243 #define CAN_RDT0R_TIME_Pos (16U)
2244 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2245 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2247 /******************* Bit definition for CAN_RDL0R register ******************/
2248 #define CAN_RDL0R_DATA0_Pos (0U)
2249 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2250 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2251 #define CAN_RDL0R_DATA1_Pos (8U)
2252 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2253 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2254 #define CAN_RDL0R_DATA2_Pos (16U)
2255 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2256 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2257 #define CAN_RDL0R_DATA3_Pos (24U)
2258 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2259 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2261 /******************* Bit definition for CAN_RDH0R register ******************/
2262 #define CAN_RDH0R_DATA4_Pos (0U)
2263 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2264 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2265 #define CAN_RDH0R_DATA5_Pos (8U)
2266 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2267 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2268 #define CAN_RDH0R_DATA6_Pos (16U)
2269 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2270 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2271 #define CAN_RDH0R_DATA7_Pos (24U)
2272 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2273 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2275 /******************* Bit definition for CAN_RI1R register *******************/
2276 #define CAN_RI1R_RTR_Pos (1U)
2277 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2278 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2279 #define CAN_RI1R_IDE_Pos (2U)
2280 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2281 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2282 #define CAN_RI1R_EXID_Pos (3U)
2283 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2284 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2285 #define CAN_RI1R_STID_Pos (21U)
2286 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2287 #define CAN_RI1R_STID CAN_RI1R_STID_Msk
2289 /******************* Bit definition for CAN_RDT1R register ******************/
2290 #define CAN_RDT1R_DLC_Pos (0U)
2291 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2292 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2293 #define CAN_RDT1R_FMI_Pos (8U)
2294 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2295 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2296 #define CAN_RDT1R_TIME_Pos (16U)
2297 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2298 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2300 /******************* Bit definition for CAN_RDL1R register ******************/
2301 #define CAN_RDL1R_DATA0_Pos (0U)
2302 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2303 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2304 #define CAN_RDL1R_DATA1_Pos (8U)
2305 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2306 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2307 #define CAN_RDL1R_DATA2_Pos (16U)
2308 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2309 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2310 #define CAN_RDL1R_DATA3_Pos (24U)
2311 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2312 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2314 /******************* Bit definition for CAN_RDH1R register ******************/
2315 #define CAN_RDH1R_DATA4_Pos (0U)
2316 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2317 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2318 #define CAN_RDH1R_DATA5_Pos (8U)
2319 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2320 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2321 #define CAN_RDH1R_DATA6_Pos (16U)
2322 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2323 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2324 #define CAN_RDH1R_DATA7_Pos (24U)
2325 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2326 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2329 /******************* Bit definition for CAN_FMR register ********************/
2330 #define CAN_FMR_FINIT_Pos (0U)
2331 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2332 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2333 #define CAN_FMR_CAN2SB_Pos (8U)
2334 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2335 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2337 /******************* Bit definition for CAN_FM1R register *******************/
2338 #define CAN_FM1R_FBM_Pos (0U)
2339 #define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2340 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2341 #define CAN_FM1R_FBM0_Pos (0U)
2342 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2343 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2344 #define CAN_FM1R_FBM1_Pos (1U)
2345 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2346 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2347 #define CAN_FM1R_FBM2_Pos (2U)
2348 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2349 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2350 #define CAN_FM1R_FBM3_Pos (3U)
2351 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2352 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2353 #define CAN_FM1R_FBM4_Pos (4U)
2354 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2355 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2356 #define CAN_FM1R_FBM5_Pos (5U)
2357 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2358 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2359 #define CAN_FM1R_FBM6_Pos (6U)
2360 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2361 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2362 #define CAN_FM1R_FBM7_Pos (7U)
2363 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2364 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2365 #define CAN_FM1R_FBM8_Pos (8U)
2366 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2367 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2368 #define CAN_FM1R_FBM9_Pos (9U)
2369 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2370 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2371 #define CAN_FM1R_FBM10_Pos (10U)
2372 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2373 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2374 #define CAN_FM1R_FBM11_Pos (11U)
2375 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2376 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2377 #define CAN_FM1R_FBM12_Pos (12U)
2378 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2379 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2380 #define CAN_FM1R_FBM13_Pos (13U)
2381 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2382 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2383 #define CAN_FM1R_FBM14_Pos (14U)
2384 #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2385 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2386 #define CAN_FM1R_FBM15_Pos (15U)
2387 #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2388 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2389 #define CAN_FM1R_FBM16_Pos (16U)
2390 #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2391 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2392 #define CAN_FM1R_FBM17_Pos (17U)
2393 #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2394 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2395 #define CAN_FM1R_FBM18_Pos (18U)
2396 #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2397 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2398 #define CAN_FM1R_FBM19_Pos (19U)
2399 #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2400 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2401 #define CAN_FM1R_FBM20_Pos (20U)
2402 #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2403 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2404 #define CAN_FM1R_FBM21_Pos (21U)
2405 #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2406 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2407 #define CAN_FM1R_FBM22_Pos (22U)
2408 #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2409 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2410 #define CAN_FM1R_FBM23_Pos (23U)
2411 #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2412 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2413 #define CAN_FM1R_FBM24_Pos (24U)
2414 #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2415 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2416 #define CAN_FM1R_FBM25_Pos (25U)
2417 #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2418 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2419 #define CAN_FM1R_FBM26_Pos (26U)
2420 #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2421 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2422 #define CAN_FM1R_FBM27_Pos (27U)
2423 #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2424 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2426 /******************* Bit definition for CAN_FS1R register *******************/
2427 #define CAN_FS1R_FSC_Pos (0U)
2428 #define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2429 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2430 #define CAN_FS1R_FSC0_Pos (0U)
2431 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2432 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2433 #define CAN_FS1R_FSC1_Pos (1U)
2434 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2435 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2436 #define CAN_FS1R_FSC2_Pos (2U)
2437 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2438 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2439 #define CAN_FS1R_FSC3_Pos (3U)
2440 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2441 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2442 #define CAN_FS1R_FSC4_Pos (4U)
2443 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2444 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2445 #define CAN_FS1R_FSC5_Pos (5U)
2446 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2447 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2448 #define CAN_FS1R_FSC6_Pos (6U)
2449 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2450 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2451 #define CAN_FS1R_FSC7_Pos (7U)
2452 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2453 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2454 #define CAN_FS1R_FSC8_Pos (8U)
2455 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2456 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2457 #define CAN_FS1R_FSC9_Pos (9U)
2458 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2459 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2460 #define CAN_FS1R_FSC10_Pos (10U)
2461 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2462 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2463 #define CAN_FS1R_FSC11_Pos (11U)
2464 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2465 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2466 #define CAN_FS1R_FSC12_Pos (12U)
2467 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2468 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2469 #define CAN_FS1R_FSC13_Pos (13U)
2470 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2471 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2472 #define CAN_FS1R_FSC14_Pos (14U)
2473 #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2474 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2475 #define CAN_FS1R_FSC15_Pos (15U)
2476 #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2477 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2478 #define CAN_FS1R_FSC16_Pos (16U)
2479 #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2480 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2481 #define CAN_FS1R_FSC17_Pos (17U)
2482 #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2483 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2484 #define CAN_FS1R_FSC18_Pos (18U)
2485 #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2486 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2487 #define CAN_FS1R_FSC19_Pos (19U)
2488 #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2489 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2490 #define CAN_FS1R_FSC20_Pos (20U)
2491 #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2492 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2493 #define CAN_FS1R_FSC21_Pos (21U)
2494 #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2495 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2496 #define CAN_FS1R_FSC22_Pos (22U)
2497 #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2498 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2499 #define CAN_FS1R_FSC23_Pos (23U)
2500 #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2501 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2502 #define CAN_FS1R_FSC24_Pos (24U)
2503 #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2504 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2505 #define CAN_FS1R_FSC25_Pos (25U)
2506 #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2507 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2508 #define CAN_FS1R_FSC26_Pos (26U)
2509 #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2510 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2511 #define CAN_FS1R_FSC27_Pos (27U)
2512 #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2513 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2515 /****************** Bit definition for CAN_FFA1R register *******************/
2516 #define CAN_FFA1R_FFA_Pos (0U)
2517 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2518 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2519 #define CAN_FFA1R_FFA0_Pos (0U)
2520 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2521 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2522 #define CAN_FFA1R_FFA1_Pos (1U)
2523 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2524 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2525 #define CAN_FFA1R_FFA2_Pos (2U)
2526 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2527 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2528 #define CAN_FFA1R_FFA3_Pos (3U)
2529 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2530 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2531 #define CAN_FFA1R_FFA4_Pos (4U)
2532 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2533 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2534 #define CAN_FFA1R_FFA5_Pos (5U)
2535 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2536 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2537 #define CAN_FFA1R_FFA6_Pos (6U)
2538 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2539 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2540 #define CAN_FFA1R_FFA7_Pos (7U)
2541 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2542 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2543 #define CAN_FFA1R_FFA8_Pos (8U)
2544 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2545 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2546 #define CAN_FFA1R_FFA9_Pos (9U)
2547 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2548 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2549 #define CAN_FFA1R_FFA10_Pos (10U)
2550 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2551 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2552 #define CAN_FFA1R_FFA11_Pos (11U)
2553 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2554 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2555 #define CAN_FFA1R_FFA12_Pos (12U)
2556 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2557 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2558 #define CAN_FFA1R_FFA13_Pos (13U)
2559 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2560 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2561 #define CAN_FFA1R_FFA14_Pos (14U)
2562 #define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2563 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2564 #define CAN_FFA1R_FFA15_Pos (15U)
2565 #define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2566 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2567 #define CAN_FFA1R_FFA16_Pos (16U)
2568 #define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2569 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2570 #define CAN_FFA1R_FFA17_Pos (17U)
2571 #define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2572 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2573 #define CAN_FFA1R_FFA18_Pos (18U)
2574 #define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2575 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2576 #define CAN_FFA1R_FFA19_Pos (19U)
2577 #define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2578 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2579 #define CAN_FFA1R_FFA20_Pos (20U)
2580 #define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2581 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2582 #define CAN_FFA1R_FFA21_Pos (21U)
2583 #define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2584 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2585 #define CAN_FFA1R_FFA22_Pos (22U)
2586 #define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2587 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2588 #define CAN_FFA1R_FFA23_Pos (23U)
2589 #define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2590 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2591 #define CAN_FFA1R_FFA24_Pos (24U)
2592 #define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2593 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2594 #define CAN_FFA1R_FFA25_Pos (25U)
2595 #define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2596 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2597 #define CAN_FFA1R_FFA26_Pos (26U)
2598 #define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2599 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2600 #define CAN_FFA1R_FFA27_Pos (27U)
2601 #define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2602 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2604 /******************* Bit definition for CAN_FA1R register *******************/
2605 #define CAN_FA1R_FACT_Pos (0U)
2606 #define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2607 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2608 #define CAN_FA1R_FACT0_Pos (0U)
2609 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2610 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2611 #define CAN_FA1R_FACT1_Pos (1U)
2612 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2613 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2614 #define CAN_FA1R_FACT2_Pos (2U)
2615 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2616 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2617 #define CAN_FA1R_FACT3_Pos (3U)
2618 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2619 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2620 #define CAN_FA1R_FACT4_Pos (4U)
2621 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2622 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2623 #define CAN_FA1R_FACT5_Pos (5U)
2624 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2625 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2626 #define CAN_FA1R_FACT6_Pos (6U)
2627 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2628 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2629 #define CAN_FA1R_FACT7_Pos (7U)
2630 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2631 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2632 #define CAN_FA1R_FACT8_Pos (8U)
2633 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2634 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2635 #define CAN_FA1R_FACT9_Pos (9U)
2636 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2637 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2638 #define CAN_FA1R_FACT10_Pos (10U)
2639 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2640 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2641 #define CAN_FA1R_FACT11_Pos (11U)
2642 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2643 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2644 #define CAN_FA1R_FACT12_Pos (12U)
2645 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2646 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2647 #define CAN_FA1R_FACT13_Pos (13U)
2648 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2649 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2650 #define CAN_FA1R_FACT14_Pos (14U)
2651 #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2652 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2653 #define CAN_FA1R_FACT15_Pos (15U)
2654 #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2655 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2656 #define CAN_FA1R_FACT16_Pos (16U)
2657 #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2658 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2659 #define CAN_FA1R_FACT17_Pos (17U)
2660 #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2661 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2662 #define CAN_FA1R_FACT18_Pos (18U)
2663 #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2664 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2665 #define CAN_FA1R_FACT19_Pos (19U)
2666 #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2667 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2668 #define CAN_FA1R_FACT20_Pos (20U)
2669 #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2670 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2671 #define CAN_FA1R_FACT21_Pos (21U)
2672 #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2673 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2674 #define CAN_FA1R_FACT22_Pos (22U)
2675 #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2676 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2677 #define CAN_FA1R_FACT23_Pos (23U)
2678 #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2679 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2680 #define CAN_FA1R_FACT24_Pos (24U)
2681 #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2682 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2683 #define CAN_FA1R_FACT25_Pos (25U)
2684 #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2685 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2686 #define CAN_FA1R_FACT26_Pos (26U)
2687 #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2688 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2689 #define CAN_FA1R_FACT27_Pos (27U)
2690 #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2691 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2694 /******************* Bit definition for CAN_F0R1 register *******************/
2695 #define CAN_F0R1_FB0_Pos (0U)
2696 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2697 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2698 #define CAN_F0R1_FB1_Pos (1U)
2699 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2700 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2701 #define CAN_F0R1_FB2_Pos (2U)
2702 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2703 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2704 #define CAN_F0R1_FB3_Pos (3U)
2705 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2706 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2707 #define CAN_F0R1_FB4_Pos (4U)
2708 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2709 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2710 #define CAN_F0R1_FB5_Pos (5U)
2711 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2712 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2713 #define CAN_F0R1_FB6_Pos (6U)
2714 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2715 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2716 #define CAN_F0R1_FB7_Pos (7U)
2717 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2718 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2719 #define CAN_F0R1_FB8_Pos (8U)
2720 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2721 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2722 #define CAN_F0R1_FB9_Pos (9U)
2723 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2724 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2725 #define CAN_F0R1_FB10_Pos (10U)
2726 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2727 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2728 #define CAN_F0R1_FB11_Pos (11U)
2729 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2730 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2731 #define CAN_F0R1_FB12_Pos (12U)
2732 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2733 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2734 #define CAN_F0R1_FB13_Pos (13U)
2735 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2736 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2737 #define CAN_F0R1_FB14_Pos (14U)
2738 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2739 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2740 #define CAN_F0R1_FB15_Pos (15U)
2741 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2742 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2743 #define CAN_F0R1_FB16_Pos (16U)
2744 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2745 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2746 #define CAN_F0R1_FB17_Pos (17U)
2747 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2748 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2749 #define CAN_F0R1_FB18_Pos (18U)
2750 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2751 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2752 #define CAN_F0R1_FB19_Pos (19U)
2753 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2754 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2755 #define CAN_F0R1_FB20_Pos (20U)
2756 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2757 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2758 #define CAN_F0R1_FB21_Pos (21U)
2759 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2760 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2761 #define CAN_F0R1_FB22_Pos (22U)
2762 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2763 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2764 #define CAN_F0R1_FB23_Pos (23U)
2765 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2766 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2767 #define CAN_F0R1_FB24_Pos (24U)
2768 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2769 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2770 #define CAN_F0R1_FB25_Pos (25U)
2771 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2772 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2773 #define CAN_F0R1_FB26_Pos (26U)
2774 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2775 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2776 #define CAN_F0R1_FB27_Pos (27U)
2777 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2778 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2779 #define CAN_F0R1_FB28_Pos (28U)
2780 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2781 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2782 #define CAN_F0R1_FB29_Pos (29U)
2783 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2784 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2785 #define CAN_F0R1_FB30_Pos (30U)
2786 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2787 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2788 #define CAN_F0R1_FB31_Pos (31U)
2789 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2790 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2792 /******************* Bit definition for CAN_F1R1 register *******************/
2793 #define CAN_F1R1_FB0_Pos (0U)
2794 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2795 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2796 #define CAN_F1R1_FB1_Pos (1U)
2797 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2798 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2799 #define CAN_F1R1_FB2_Pos (2U)
2800 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2801 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2802 #define CAN_F1R1_FB3_Pos (3U)
2803 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2804 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2805 #define CAN_F1R1_FB4_Pos (4U)
2806 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2807 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2808 #define CAN_F1R1_FB5_Pos (5U)
2809 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2810 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2811 #define CAN_F1R1_FB6_Pos (6U)
2812 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2813 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2814 #define CAN_F1R1_FB7_Pos (7U)
2815 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2816 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2817 #define CAN_F1R1_FB8_Pos (8U)
2818 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2819 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2820 #define CAN_F1R1_FB9_Pos (9U)
2821 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2822 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2823 #define CAN_F1R1_FB10_Pos (10U)
2824 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2825 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2826 #define CAN_F1R1_FB11_Pos (11U)
2827 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2828 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2829 #define CAN_F1R1_FB12_Pos (12U)
2830 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2831 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2832 #define CAN_F1R1_FB13_Pos (13U)
2833 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2834 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2835 #define CAN_F1R1_FB14_Pos (14U)
2836 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2837 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2838 #define CAN_F1R1_FB15_Pos (15U)
2839 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2840 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2841 #define CAN_F1R1_FB16_Pos (16U)
2842 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2843 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2844 #define CAN_F1R1_FB17_Pos (17U)
2845 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2846 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2847 #define CAN_F1R1_FB18_Pos (18U)
2848 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2849 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2850 #define CAN_F1R1_FB19_Pos (19U)
2851 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2852 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2853 #define CAN_F1R1_FB20_Pos (20U)
2854 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2855 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2856 #define CAN_F1R1_FB21_Pos (21U)
2857 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2858 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2859 #define CAN_F1R1_FB22_Pos (22U)
2860 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2861 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2862 #define CAN_F1R1_FB23_Pos (23U)
2863 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2864 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2865 #define CAN_F1R1_FB24_Pos (24U)
2866 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2867 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2868 #define CAN_F1R1_FB25_Pos (25U)
2869 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2870 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2871 #define CAN_F1R1_FB26_Pos (26U)
2872 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2873 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2874 #define CAN_F1R1_FB27_Pos (27U)
2875 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2876 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2877 #define CAN_F1R1_FB28_Pos (28U)
2878 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2879 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2880 #define CAN_F1R1_FB29_Pos (29U)
2881 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2882 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2883 #define CAN_F1R1_FB30_Pos (30U)
2884 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2885 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2886 #define CAN_F1R1_FB31_Pos (31U)
2887 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2888 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2890 /******************* Bit definition for CAN_F2R1 register *******************/
2891 #define CAN_F2R1_FB0_Pos (0U)
2892 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2893 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2894 #define CAN_F2R1_FB1_Pos (1U)
2895 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2896 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2897 #define CAN_F2R1_FB2_Pos (2U)
2898 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2899 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2900 #define CAN_F2R1_FB3_Pos (3U)
2901 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2902 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2903 #define CAN_F2R1_FB4_Pos (4U)
2904 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2905 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2906 #define CAN_F2R1_FB5_Pos (5U)
2907 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2908 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2909 #define CAN_F2R1_FB6_Pos (6U)
2910 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2911 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2912 #define CAN_F2R1_FB7_Pos (7U)
2913 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2914 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2915 #define CAN_F2R1_FB8_Pos (8U)
2916 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2917 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2918 #define CAN_F2R1_FB9_Pos (9U)
2919 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2920 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2921 #define CAN_F2R1_FB10_Pos (10U)
2922 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2923 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2924 #define CAN_F2R1_FB11_Pos (11U)
2925 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2926 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2927 #define CAN_F2R1_FB12_Pos (12U)
2928 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2929 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2930 #define CAN_F2R1_FB13_Pos (13U)
2931 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2932 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2933 #define CAN_F2R1_FB14_Pos (14U)
2934 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2935 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2936 #define CAN_F2R1_FB15_Pos (15U)
2937 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2938 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2939 #define CAN_F2R1_FB16_Pos (16U)
2940 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2941 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2942 #define CAN_F2R1_FB17_Pos (17U)
2943 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2944 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2945 #define CAN_F2R1_FB18_Pos (18U)
2946 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2947 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2948 #define CAN_F2R1_FB19_Pos (19U)
2949 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2950 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2951 #define CAN_F2R1_FB20_Pos (20U)
2952 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2953 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2954 #define CAN_F2R1_FB21_Pos (21U)
2955 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2956 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2957 #define CAN_F2R1_FB22_Pos (22U)
2958 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2959 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2960 #define CAN_F2R1_FB23_Pos (23U)
2961 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2962 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2963 #define CAN_F2R1_FB24_Pos (24U)
2964 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2965 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2966 #define CAN_F2R1_FB25_Pos (25U)
2967 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2968 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2969 #define CAN_F2R1_FB26_Pos (26U)
2970 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2971 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2972 #define CAN_F2R1_FB27_Pos (27U)
2973 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2974 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2975 #define CAN_F2R1_FB28_Pos (28U)
2976 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2977 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2978 #define CAN_F2R1_FB29_Pos (29U)
2979 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2980 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2981 #define CAN_F2R1_FB30_Pos (30U)
2982 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2983 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2984 #define CAN_F2R1_FB31_Pos (31U)
2985 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2986 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2988 /******************* Bit definition for CAN_F3R1 register *******************/
2989 #define CAN_F3R1_FB0_Pos (0U)
2990 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2991 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2992 #define CAN_F3R1_FB1_Pos (1U)
2993 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2994 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2995 #define CAN_F3R1_FB2_Pos (2U)
2996 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2997 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2998 #define CAN_F3R1_FB3_Pos (3U)
2999 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3000 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3001 #define CAN_F3R1_FB4_Pos (4U)
3002 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3003 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3004 #define CAN_F3R1_FB5_Pos (5U)
3005 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3006 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3007 #define CAN_F3R1_FB6_Pos (6U)
3008 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3009 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3010 #define CAN_F3R1_FB7_Pos (7U)
3011 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3012 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3013 #define CAN_F3R1_FB8_Pos (8U)
3014 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3015 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3016 #define CAN_F3R1_FB9_Pos (9U)
3017 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3018 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3019 #define CAN_F3R1_FB10_Pos (10U)
3020 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3021 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3022 #define CAN_F3R1_FB11_Pos (11U)
3023 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3024 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3025 #define CAN_F3R1_FB12_Pos (12U)
3026 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3027 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3028 #define CAN_F3R1_FB13_Pos (13U)
3029 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3030 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3031 #define CAN_F3R1_FB14_Pos (14U)
3032 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3033 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3034 #define CAN_F3R1_FB15_Pos (15U)
3035 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3036 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3037 #define CAN_F3R1_FB16_Pos (16U)
3038 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3039 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3040 #define CAN_F3R1_FB17_Pos (17U)
3041 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3042 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3043 #define CAN_F3R1_FB18_Pos (18U)
3044 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3045 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3046 #define CAN_F3R1_FB19_Pos (19U)
3047 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3048 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3049 #define CAN_F3R1_FB20_Pos (20U)
3050 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3051 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3052 #define CAN_F3R1_FB21_Pos (21U)
3053 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3054 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3055 #define CAN_F3R1_FB22_Pos (22U)
3056 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3057 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3058 #define CAN_F3R1_FB23_Pos (23U)
3059 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3060 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3061 #define CAN_F3R1_FB24_Pos (24U)
3062 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3063 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3064 #define CAN_F3R1_FB25_Pos (25U)
3065 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3066 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3067 #define CAN_F3R1_FB26_Pos (26U)
3068 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3069 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3070 #define CAN_F3R1_FB27_Pos (27U)
3071 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3072 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3073 #define CAN_F3R1_FB28_Pos (28U)
3074 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3075 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3076 #define CAN_F3R1_FB29_Pos (29U)
3077 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3078 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3079 #define CAN_F3R1_FB30_Pos (30U)
3080 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3081 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3082 #define CAN_F3R1_FB31_Pos (31U)
3083 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3084 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3086 /******************* Bit definition for CAN_F4R1 register *******************/
3087 #define CAN_F4R1_FB0_Pos (0U)
3088 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3089 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3090 #define CAN_F4R1_FB1_Pos (1U)
3091 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3092 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3093 #define CAN_F4R1_FB2_Pos (2U)
3094 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3095 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3096 #define CAN_F4R1_FB3_Pos (3U)
3097 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3098 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3099 #define CAN_F4R1_FB4_Pos (4U)
3100 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3101 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3102 #define CAN_F4R1_FB5_Pos (5U)
3103 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3104 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3105 #define CAN_F4R1_FB6_Pos (6U)
3106 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3107 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3108 #define CAN_F4R1_FB7_Pos (7U)
3109 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3110 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3111 #define CAN_F4R1_FB8_Pos (8U)
3112 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3113 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3114 #define CAN_F4R1_FB9_Pos (9U)
3115 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3116 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3117 #define CAN_F4R1_FB10_Pos (10U)
3118 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3119 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3120 #define CAN_F4R1_FB11_Pos (11U)
3121 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3122 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3123 #define CAN_F4R1_FB12_Pos (12U)
3124 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3125 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3126 #define CAN_F4R1_FB13_Pos (13U)
3127 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3128 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3129 #define CAN_F4R1_FB14_Pos (14U)
3130 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3131 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3132 #define CAN_F4R1_FB15_Pos (15U)
3133 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3134 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3135 #define CAN_F4R1_FB16_Pos (16U)
3136 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3137 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3138 #define CAN_F4R1_FB17_Pos (17U)
3139 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3140 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3141 #define CAN_F4R1_FB18_Pos (18U)
3142 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3143 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3144 #define CAN_F4R1_FB19_Pos (19U)
3145 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3146 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3147 #define CAN_F4R1_FB20_Pos (20U)
3148 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3149 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3150 #define CAN_F4R1_FB21_Pos (21U)
3151 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3152 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3153 #define CAN_F4R1_FB22_Pos (22U)
3154 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3155 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3156 #define CAN_F4R1_FB23_Pos (23U)
3157 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3158 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3159 #define CAN_F4R1_FB24_Pos (24U)
3160 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3161 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3162 #define CAN_F4R1_FB25_Pos (25U)
3163 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3164 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3165 #define CAN_F4R1_FB26_Pos (26U)
3166 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3167 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3168 #define CAN_F4R1_FB27_Pos (27U)
3169 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3170 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3171 #define CAN_F4R1_FB28_Pos (28U)
3172 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3173 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3174 #define CAN_F4R1_FB29_Pos (29U)
3175 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3176 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3177 #define CAN_F4R1_FB30_Pos (30U)
3178 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3179 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3180 #define CAN_F4R1_FB31_Pos (31U)
3181 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3182 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3184 /******************* Bit definition for CAN_F5R1 register *******************/
3185 #define CAN_F5R1_FB0_Pos (0U)
3186 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3187 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3188 #define CAN_F5R1_FB1_Pos (1U)
3189 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3190 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3191 #define CAN_F5R1_FB2_Pos (2U)
3192 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3193 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3194 #define CAN_F5R1_FB3_Pos (3U)
3195 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3196 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3197 #define CAN_F5R1_FB4_Pos (4U)
3198 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3199 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3200 #define CAN_F5R1_FB5_Pos (5U)
3201 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3202 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3203 #define CAN_F5R1_FB6_Pos (6U)
3204 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3205 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3206 #define CAN_F5R1_FB7_Pos (7U)
3207 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3208 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3209 #define CAN_F5R1_FB8_Pos (8U)
3210 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3211 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3212 #define CAN_F5R1_FB9_Pos (9U)
3213 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3214 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3215 #define CAN_F5R1_FB10_Pos (10U)
3216 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3217 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3218 #define CAN_F5R1_FB11_Pos (11U)
3219 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3220 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3221 #define CAN_F5R1_FB12_Pos (12U)
3222 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3223 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3224 #define CAN_F5R1_FB13_Pos (13U)
3225 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3226 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3227 #define CAN_F5R1_FB14_Pos (14U)
3228 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3229 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3230 #define CAN_F5R1_FB15_Pos (15U)
3231 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3232 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3233 #define CAN_F5R1_FB16_Pos (16U)
3234 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3235 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3236 #define CAN_F5R1_FB17_Pos (17U)
3237 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3238 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3239 #define CAN_F5R1_FB18_Pos (18U)
3240 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3241 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3242 #define CAN_F5R1_FB19_Pos (19U)
3243 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3244 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3245 #define CAN_F5R1_FB20_Pos (20U)
3246 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3247 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3248 #define CAN_F5R1_FB21_Pos (21U)
3249 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3250 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3251 #define CAN_F5R1_FB22_Pos (22U)
3252 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3253 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3254 #define CAN_F5R1_FB23_Pos (23U)
3255 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3256 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3257 #define CAN_F5R1_FB24_Pos (24U)
3258 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3259 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3260 #define CAN_F5R1_FB25_Pos (25U)
3261 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3262 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3263 #define CAN_F5R1_FB26_Pos (26U)
3264 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3265 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3266 #define CAN_F5R1_FB27_Pos (27U)
3267 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3268 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3269 #define CAN_F5R1_FB28_Pos (28U)
3270 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3271 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3272 #define CAN_F5R1_FB29_Pos (29U)
3273 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3274 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3275 #define CAN_F5R1_FB30_Pos (30U)
3276 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3277 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3278 #define CAN_F5R1_FB31_Pos (31U)
3279 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3280 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3282 /******************* Bit definition for CAN_F6R1 register *******************/
3283 #define CAN_F6R1_FB0_Pos (0U)
3284 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3285 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3286 #define CAN_F6R1_FB1_Pos (1U)
3287 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3288 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3289 #define CAN_F6R1_FB2_Pos (2U)
3290 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3291 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3292 #define CAN_F6R1_FB3_Pos (3U)
3293 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3294 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3295 #define CAN_F6R1_FB4_Pos (4U)
3296 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3297 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3298 #define CAN_F6R1_FB5_Pos (5U)
3299 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3300 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3301 #define CAN_F6R1_FB6_Pos (6U)
3302 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3303 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3304 #define CAN_F6R1_FB7_Pos (7U)
3305 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3306 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3307 #define CAN_F6R1_FB8_Pos (8U)
3308 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3309 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3310 #define CAN_F6R1_FB9_Pos (9U)
3311 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3312 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3313 #define CAN_F6R1_FB10_Pos (10U)
3314 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3315 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3316 #define CAN_F6R1_FB11_Pos (11U)
3317 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3318 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3319 #define CAN_F6R1_FB12_Pos (12U)
3320 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3321 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3322 #define CAN_F6R1_FB13_Pos (13U)
3323 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3324 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3325 #define CAN_F6R1_FB14_Pos (14U)
3326 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3327 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3328 #define CAN_F6R1_FB15_Pos (15U)
3329 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3330 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3331 #define CAN_F6R1_FB16_Pos (16U)
3332 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3333 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3334 #define CAN_F6R1_FB17_Pos (17U)
3335 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3336 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3337 #define CAN_F6R1_FB18_Pos (18U)
3338 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3339 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3340 #define CAN_F6R1_FB19_Pos (19U)
3341 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3342 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3343 #define CAN_F6R1_FB20_Pos (20U)
3344 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3345 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3346 #define CAN_F6R1_FB21_Pos (21U)
3347 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3348 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3349 #define CAN_F6R1_FB22_Pos (22U)
3350 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3351 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3352 #define CAN_F6R1_FB23_Pos (23U)
3353 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3354 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3355 #define CAN_F6R1_FB24_Pos (24U)
3356 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3357 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3358 #define CAN_F6R1_FB25_Pos (25U)
3359 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3360 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3361 #define CAN_F6R1_FB26_Pos (26U)
3362 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3363 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3364 #define CAN_F6R1_FB27_Pos (27U)
3365 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3366 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3367 #define CAN_F6R1_FB28_Pos (28U)
3368 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3369 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3370 #define CAN_F6R1_FB29_Pos (29U)
3371 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3372 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3373 #define CAN_F6R1_FB30_Pos (30U)
3374 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3375 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3376 #define CAN_F6R1_FB31_Pos (31U)
3377 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3378 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3380 /******************* Bit definition for CAN_F7R1 register *******************/
3381 #define CAN_F7R1_FB0_Pos (0U)
3382 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3383 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3384 #define CAN_F7R1_FB1_Pos (1U)
3385 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3386 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3387 #define CAN_F7R1_FB2_Pos (2U)
3388 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3389 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3390 #define CAN_F7R1_FB3_Pos (3U)
3391 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3392 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3393 #define CAN_F7R1_FB4_Pos (4U)
3394 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3395 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3396 #define CAN_F7R1_FB5_Pos (5U)
3397 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3398 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3399 #define CAN_F7R1_FB6_Pos (6U)
3400 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3401 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3402 #define CAN_F7R1_FB7_Pos (7U)
3403 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3404 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3405 #define CAN_F7R1_FB8_Pos (8U)
3406 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3407 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3408 #define CAN_F7R1_FB9_Pos (9U)
3409 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3410 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3411 #define CAN_F7R1_FB10_Pos (10U)
3412 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3413 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3414 #define CAN_F7R1_FB11_Pos (11U)
3415 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3416 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3417 #define CAN_F7R1_FB12_Pos (12U)
3418 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3419 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3420 #define CAN_F7R1_FB13_Pos (13U)
3421 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3422 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3423 #define CAN_F7R1_FB14_Pos (14U)
3424 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3425 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3426 #define CAN_F7R1_FB15_Pos (15U)
3427 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3428 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3429 #define CAN_F7R1_FB16_Pos (16U)
3430 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3431 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3432 #define CAN_F7R1_FB17_Pos (17U)
3433 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3434 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3435 #define CAN_F7R1_FB18_Pos (18U)
3436 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3437 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3438 #define CAN_F7R1_FB19_Pos (19U)
3439 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3440 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3441 #define CAN_F7R1_FB20_Pos (20U)
3442 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3443 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3444 #define CAN_F7R1_FB21_Pos (21U)
3445 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3446 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3447 #define CAN_F7R1_FB22_Pos (22U)
3448 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3449 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3450 #define CAN_F7R1_FB23_Pos (23U)
3451 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3452 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3453 #define CAN_F7R1_FB24_Pos (24U)
3454 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3455 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3456 #define CAN_F7R1_FB25_Pos (25U)
3457 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3458 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3459 #define CAN_F7R1_FB26_Pos (26U)
3460 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3461 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3462 #define CAN_F7R1_FB27_Pos (27U)
3463 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3464 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3465 #define CAN_F7R1_FB28_Pos (28U)
3466 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3467 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3468 #define CAN_F7R1_FB29_Pos (29U)
3469 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3470 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3471 #define CAN_F7R1_FB30_Pos (30U)
3472 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3473 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3474 #define CAN_F7R1_FB31_Pos (31U)
3475 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3476 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3478 /******************* Bit definition for CAN_F8R1 register *******************/
3479 #define CAN_F8R1_FB0_Pos (0U)
3480 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3481 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3482 #define CAN_F8R1_FB1_Pos (1U)
3483 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3484 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3485 #define CAN_F8R1_FB2_Pos (2U)
3486 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3487 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3488 #define CAN_F8R1_FB3_Pos (3U)
3489 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3490 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3491 #define CAN_F8R1_FB4_Pos (4U)
3492 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3493 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3494 #define CAN_F8R1_FB5_Pos (5U)
3495 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3496 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3497 #define CAN_F8R1_FB6_Pos (6U)
3498 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3499 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3500 #define CAN_F8R1_FB7_Pos (7U)
3501 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3502 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3503 #define CAN_F8R1_FB8_Pos (8U)
3504 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3505 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3506 #define CAN_F8R1_FB9_Pos (9U)
3507 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3508 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3509 #define CAN_F8R1_FB10_Pos (10U)
3510 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3511 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3512 #define CAN_F8R1_FB11_Pos (11U)
3513 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3514 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3515 #define CAN_F8R1_FB12_Pos (12U)
3516 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3517 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3518 #define CAN_F8R1_FB13_Pos (13U)
3519 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3520 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3521 #define CAN_F8R1_FB14_Pos (14U)
3522 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3523 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3524 #define CAN_F8R1_FB15_Pos (15U)
3525 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3526 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3527 #define CAN_F8R1_FB16_Pos (16U)
3528 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3529 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3530 #define CAN_F8R1_FB17_Pos (17U)
3531 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3532 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3533 #define CAN_F8R1_FB18_Pos (18U)
3534 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3535 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3536 #define CAN_F8R1_FB19_Pos (19U)
3537 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3538 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3539 #define CAN_F8R1_FB20_Pos (20U)
3540 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3541 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3542 #define CAN_F8R1_FB21_Pos (21U)
3543 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3544 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3545 #define CAN_F8R1_FB22_Pos (22U)
3546 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3547 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3548 #define CAN_F8R1_FB23_Pos (23U)
3549 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3550 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3551 #define CAN_F8R1_FB24_Pos (24U)
3552 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3553 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3554 #define CAN_F8R1_FB25_Pos (25U)
3555 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3556 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3557 #define CAN_F8R1_FB26_Pos (26U)
3558 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3559 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3560 #define CAN_F8R1_FB27_Pos (27U)
3561 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3562 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3563 #define CAN_F8R1_FB28_Pos (28U)
3564 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3565 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3566 #define CAN_F8R1_FB29_Pos (29U)
3567 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3568 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3569 #define CAN_F8R1_FB30_Pos (30U)
3570 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3571 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3572 #define CAN_F8R1_FB31_Pos (31U)
3573 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3574 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3576 /******************* Bit definition for CAN_F9R1 register *******************/
3577 #define CAN_F9R1_FB0_Pos (0U)
3578 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3579 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3580 #define CAN_F9R1_FB1_Pos (1U)
3581 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3582 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3583 #define CAN_F9R1_FB2_Pos (2U)
3584 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3585 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3586 #define CAN_F9R1_FB3_Pos (3U)
3587 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3588 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3589 #define CAN_F9R1_FB4_Pos (4U)
3590 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3591 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3592 #define CAN_F9R1_FB5_Pos (5U)
3593 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3594 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3595 #define CAN_F9R1_FB6_Pos (6U)
3596 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3597 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3598 #define CAN_F9R1_FB7_Pos (7U)
3599 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3600 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3601 #define CAN_F9R1_FB8_Pos (8U)
3602 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3603 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3604 #define CAN_F9R1_FB9_Pos (9U)
3605 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3606 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3607 #define CAN_F9R1_FB10_Pos (10U)
3608 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3609 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3610 #define CAN_F9R1_FB11_Pos (11U)
3611 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3612 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3613 #define CAN_F9R1_FB12_Pos (12U)
3614 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3615 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3616 #define CAN_F9R1_FB13_Pos (13U)
3617 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3618 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3619 #define CAN_F9R1_FB14_Pos (14U)
3620 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3621 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3622 #define CAN_F9R1_FB15_Pos (15U)
3623 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3624 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3625 #define CAN_F9R1_FB16_Pos (16U)
3626 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3627 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3628 #define CAN_F9R1_FB17_Pos (17U)
3629 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3630 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3631 #define CAN_F9R1_FB18_Pos (18U)
3632 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3633 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3634 #define CAN_F9R1_FB19_Pos (19U)
3635 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3636 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3637 #define CAN_F9R1_FB20_Pos (20U)
3638 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3639 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3640 #define CAN_F9R1_FB21_Pos (21U)
3641 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3642 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3643 #define CAN_F9R1_FB22_Pos (22U)
3644 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3645 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3646 #define CAN_F9R1_FB23_Pos (23U)
3647 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3648 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3649 #define CAN_F9R1_FB24_Pos (24U)
3650 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3651 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3652 #define CAN_F9R1_FB25_Pos (25U)
3653 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3654 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3655 #define CAN_F9R1_FB26_Pos (26U)
3656 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3657 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3658 #define CAN_F9R1_FB27_Pos (27U)
3659 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3660 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3661 #define CAN_F9R1_FB28_Pos (28U)
3662 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3663 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3664 #define CAN_F9R1_FB29_Pos (29U)
3665 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3666 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3667 #define CAN_F9R1_FB30_Pos (30U)
3668 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3669 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3670 #define CAN_F9R1_FB31_Pos (31U)
3671 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3672 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3674 /******************* Bit definition for CAN_F10R1 register ******************/
3675 #define CAN_F10R1_FB0_Pos (0U)
3676 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3677 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3678 #define CAN_F10R1_FB1_Pos (1U)
3679 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3680 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3681 #define CAN_F10R1_FB2_Pos (2U)
3682 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3683 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3684 #define CAN_F10R1_FB3_Pos (3U)
3685 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3686 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3687 #define CAN_F10R1_FB4_Pos (4U)
3688 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3689 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3690 #define CAN_F10R1_FB5_Pos (5U)
3691 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3692 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3693 #define CAN_F10R1_FB6_Pos (6U)
3694 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3695 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3696 #define CAN_F10R1_FB7_Pos (7U)
3697 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3698 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3699 #define CAN_F10R1_FB8_Pos (8U)
3700 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3701 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3702 #define CAN_F10R1_FB9_Pos (9U)
3703 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3704 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3705 #define CAN_F10R1_FB10_Pos (10U)
3706 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3707 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3708 #define CAN_F10R1_FB11_Pos (11U)
3709 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3710 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3711 #define CAN_F10R1_FB12_Pos (12U)
3712 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3713 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3714 #define CAN_F10R1_FB13_Pos (13U)
3715 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3716 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3717 #define CAN_F10R1_FB14_Pos (14U)
3718 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3719 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3720 #define CAN_F10R1_FB15_Pos (15U)
3721 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3722 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3723 #define CAN_F10R1_FB16_Pos (16U)
3724 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3725 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3726 #define CAN_F10R1_FB17_Pos (17U)
3727 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3728 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3729 #define CAN_F10R1_FB18_Pos (18U)
3730 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3731 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3732 #define CAN_F10R1_FB19_Pos (19U)
3733 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3734 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3735 #define CAN_F10R1_FB20_Pos (20U)
3736 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3737 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3738 #define CAN_F10R1_FB21_Pos (21U)
3739 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3740 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3741 #define CAN_F10R1_FB22_Pos (22U)
3742 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3743 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3744 #define CAN_F10R1_FB23_Pos (23U)
3745 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3746 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3747 #define CAN_F10R1_FB24_Pos (24U)
3748 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3749 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3750 #define CAN_F10R1_FB25_Pos (25U)
3751 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3752 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3753 #define CAN_F10R1_FB26_Pos (26U)
3754 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3755 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3756 #define CAN_F10R1_FB27_Pos (27U)
3757 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3758 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3759 #define CAN_F10R1_FB28_Pos (28U)
3760 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3761 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3762 #define CAN_F10R1_FB29_Pos (29U)
3763 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3764 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3765 #define CAN_F10R1_FB30_Pos (30U)
3766 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3767 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3768 #define CAN_F10R1_FB31_Pos (31U)
3769 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3770 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3772 /******************* Bit definition for CAN_F11R1 register ******************/
3773 #define CAN_F11R1_FB0_Pos (0U)
3774 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3775 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3776 #define CAN_F11R1_FB1_Pos (1U)
3777 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3778 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3779 #define CAN_F11R1_FB2_Pos (2U)
3780 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3781 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3782 #define CAN_F11R1_FB3_Pos (3U)
3783 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3784 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3785 #define CAN_F11R1_FB4_Pos (4U)
3786 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3787 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3788 #define CAN_F11R1_FB5_Pos (5U)
3789 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3790 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3791 #define CAN_F11R1_FB6_Pos (6U)
3792 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3793 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3794 #define CAN_F11R1_FB7_Pos (7U)
3795 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3796 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3797 #define CAN_F11R1_FB8_Pos (8U)
3798 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3799 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3800 #define CAN_F11R1_FB9_Pos (9U)
3801 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3802 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3803 #define CAN_F11R1_FB10_Pos (10U)
3804 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3805 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3806 #define CAN_F11R1_FB11_Pos (11U)
3807 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3808 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3809 #define CAN_F11R1_FB12_Pos (12U)
3810 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3811 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3812 #define CAN_F11R1_FB13_Pos (13U)
3813 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3814 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3815 #define CAN_F11R1_FB14_Pos (14U)
3816 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3817 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3818 #define CAN_F11R1_FB15_Pos (15U)
3819 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3820 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3821 #define CAN_F11R1_FB16_Pos (16U)
3822 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3823 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3824 #define CAN_F11R1_FB17_Pos (17U)
3825 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3826 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3827 #define CAN_F11R1_FB18_Pos (18U)
3828 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3829 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3830 #define CAN_F11R1_FB19_Pos (19U)
3831 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3832 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3833 #define CAN_F11R1_FB20_Pos (20U)
3834 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3835 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3836 #define CAN_F11R1_FB21_Pos (21U)
3837 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3838 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3839 #define CAN_F11R1_FB22_Pos (22U)
3840 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3841 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3842 #define CAN_F11R1_FB23_Pos (23U)
3843 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3844 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3845 #define CAN_F11R1_FB24_Pos (24U)
3846 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3847 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3848 #define CAN_F11R1_FB25_Pos (25U)
3849 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3850 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3851 #define CAN_F11R1_FB26_Pos (26U)
3852 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3853 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3854 #define CAN_F11R1_FB27_Pos (27U)
3855 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3856 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3857 #define CAN_F11R1_FB28_Pos (28U)
3858 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3859 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3860 #define CAN_F11R1_FB29_Pos (29U)
3861 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3862 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3863 #define CAN_F11R1_FB30_Pos (30U)
3864 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3865 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3866 #define CAN_F11R1_FB31_Pos (31U)
3867 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3868 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3870 /******************* Bit definition for CAN_F12R1 register ******************/
3871 #define CAN_F12R1_FB0_Pos (0U)
3872 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3873 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3874 #define CAN_F12R1_FB1_Pos (1U)
3875 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3876 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3877 #define CAN_F12R1_FB2_Pos (2U)
3878 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3879 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3880 #define CAN_F12R1_FB3_Pos (3U)
3881 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3882 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3883 #define CAN_F12R1_FB4_Pos (4U)
3884 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3885 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3886 #define CAN_F12R1_FB5_Pos (5U)
3887 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3888 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3889 #define CAN_F12R1_FB6_Pos (6U)
3890 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3891 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3892 #define CAN_F12R1_FB7_Pos (7U)
3893 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3894 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3895 #define CAN_F12R1_FB8_Pos (8U)
3896 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3897 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3898 #define CAN_F12R1_FB9_Pos (9U)
3899 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3900 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3901 #define CAN_F12R1_FB10_Pos (10U)
3902 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3903 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3904 #define CAN_F12R1_FB11_Pos (11U)
3905 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3906 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3907 #define CAN_F12R1_FB12_Pos (12U)
3908 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3909 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3910 #define CAN_F12R1_FB13_Pos (13U)
3911 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3912 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3913 #define CAN_F12R1_FB14_Pos (14U)
3914 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3915 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3916 #define CAN_F12R1_FB15_Pos (15U)
3917 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3918 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3919 #define CAN_F12R1_FB16_Pos (16U)
3920 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3921 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3922 #define CAN_F12R1_FB17_Pos (17U)
3923 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3924 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3925 #define CAN_F12R1_FB18_Pos (18U)
3926 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3927 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3928 #define CAN_F12R1_FB19_Pos (19U)
3929 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3930 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3931 #define CAN_F12R1_FB20_Pos (20U)
3932 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3933 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3934 #define CAN_F12R1_FB21_Pos (21U)
3935 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3936 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3937 #define CAN_F12R1_FB22_Pos (22U)
3938 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3939 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3940 #define CAN_F12R1_FB23_Pos (23U)
3941 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3942 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3943 #define CAN_F12R1_FB24_Pos (24U)
3944 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3945 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3946 #define CAN_F12R1_FB25_Pos (25U)
3947 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3948 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3949 #define CAN_F12R1_FB26_Pos (26U)
3950 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3951 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3952 #define CAN_F12R1_FB27_Pos (27U)
3953 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3954 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3955 #define CAN_F12R1_FB28_Pos (28U)
3956 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3957 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3958 #define CAN_F12R1_FB29_Pos (29U)
3959 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3960 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3961 #define CAN_F12R1_FB30_Pos (30U)
3962 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3963 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3964 #define CAN_F12R1_FB31_Pos (31U)
3965 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3966 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3968 /******************* Bit definition for CAN_F13R1 register ******************/
3969 #define CAN_F13R1_FB0_Pos (0U)
3970 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3971 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3972 #define CAN_F13R1_FB1_Pos (1U)
3973 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3974 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3975 #define CAN_F13R1_FB2_Pos (2U)
3976 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3977 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3978 #define CAN_F13R1_FB3_Pos (3U)
3979 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3980 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3981 #define CAN_F13R1_FB4_Pos (4U)
3982 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3983 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3984 #define CAN_F13R1_FB5_Pos (5U)
3985 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3986 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3987 #define CAN_F13R1_FB6_Pos (6U)
3988 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3989 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3990 #define CAN_F13R1_FB7_Pos (7U)
3991 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3992 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3993 #define CAN_F13R1_FB8_Pos (8U)
3994 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3995 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3996 #define CAN_F13R1_FB9_Pos (9U)
3997 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3998 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3999 #define CAN_F13R1_FB10_Pos (10U)
4000 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4001 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4002 #define CAN_F13R1_FB11_Pos (11U)
4003 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4004 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4005 #define CAN_F13R1_FB12_Pos (12U)
4006 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4007 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4008 #define CAN_F13R1_FB13_Pos (13U)
4009 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4010 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4011 #define CAN_F13R1_FB14_Pos (14U)
4012 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4013 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4014 #define CAN_F13R1_FB15_Pos (15U)
4015 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4016 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4017 #define CAN_F13R1_FB16_Pos (16U)
4018 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4019 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4020 #define CAN_F13R1_FB17_Pos (17U)
4021 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4022 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4023 #define CAN_F13R1_FB18_Pos (18U)
4024 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4025 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4026 #define CAN_F13R1_FB19_Pos (19U)
4027 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4028 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4029 #define CAN_F13R1_FB20_Pos (20U)
4030 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4031 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4032 #define CAN_F13R1_FB21_Pos (21U)
4033 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4034 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4035 #define CAN_F13R1_FB22_Pos (22U)
4036 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4037 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4038 #define CAN_F13R1_FB23_Pos (23U)
4039 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4040 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4041 #define CAN_F13R1_FB24_Pos (24U)
4042 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4043 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4044 #define CAN_F13R1_FB25_Pos (25U)
4045 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4046 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4047 #define CAN_F13R1_FB26_Pos (26U)
4048 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4049 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4050 #define CAN_F13R1_FB27_Pos (27U)
4051 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4052 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4053 #define CAN_F13R1_FB28_Pos (28U)
4054 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4055 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4056 #define CAN_F13R1_FB29_Pos (29U)
4057 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4058 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4059 #define CAN_F13R1_FB30_Pos (30U)
4060 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4061 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4062 #define CAN_F13R1_FB31_Pos (31U)
4063 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4064 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4066 /******************* Bit definition for CAN_F0R2 register *******************/
4067 #define CAN_F0R2_FB0_Pos (0U)
4068 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4069 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4070 #define CAN_F0R2_FB1_Pos (1U)
4071 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4072 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4073 #define CAN_F0R2_FB2_Pos (2U)
4074 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4075 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4076 #define CAN_F0R2_FB3_Pos (3U)
4077 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4078 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4079 #define CAN_F0R2_FB4_Pos (4U)
4080 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4081 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4082 #define CAN_F0R2_FB5_Pos (5U)
4083 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4084 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4085 #define CAN_F0R2_FB6_Pos (6U)
4086 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4087 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4088 #define CAN_F0R2_FB7_Pos (7U)
4089 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4090 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4091 #define CAN_F0R2_FB8_Pos (8U)
4092 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4093 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4094 #define CAN_F0R2_FB9_Pos (9U)
4095 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4096 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4097 #define CAN_F0R2_FB10_Pos (10U)
4098 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4099 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4100 #define CAN_F0R2_FB11_Pos (11U)
4101 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4102 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4103 #define CAN_F0R2_FB12_Pos (12U)
4104 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4105 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4106 #define CAN_F0R2_FB13_Pos (13U)
4107 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4108 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4109 #define CAN_F0R2_FB14_Pos (14U)
4110 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4111 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4112 #define CAN_F0R2_FB15_Pos (15U)
4113 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4114 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4115 #define CAN_F0R2_FB16_Pos (16U)
4116 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4117 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4118 #define CAN_F0R2_FB17_Pos (17U)
4119 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4120 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4121 #define CAN_F0R2_FB18_Pos (18U)
4122 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4123 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4124 #define CAN_F0R2_FB19_Pos (19U)
4125 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4126 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4127 #define CAN_F0R2_FB20_Pos (20U)
4128 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4129 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4130 #define CAN_F0R2_FB21_Pos (21U)
4131 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4132 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4133 #define CAN_F0R2_FB22_Pos (22U)
4134 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4135 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4136 #define CAN_F0R2_FB23_Pos (23U)
4137 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4138 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4139 #define CAN_F0R2_FB24_Pos (24U)
4140 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4141 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4142 #define CAN_F0R2_FB25_Pos (25U)
4143 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4144 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4145 #define CAN_F0R2_FB26_Pos (26U)
4146 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4147 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4148 #define CAN_F0R2_FB27_Pos (27U)
4149 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4150 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4151 #define CAN_F0R2_FB28_Pos (28U)
4152 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4153 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4154 #define CAN_F0R2_FB29_Pos (29U)
4155 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4156 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4157 #define CAN_F0R2_FB30_Pos (30U)
4158 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4159 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4160 #define CAN_F0R2_FB31_Pos (31U)
4161 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4162 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4164 /******************* Bit definition for CAN_F1R2 register *******************/
4165 #define CAN_F1R2_FB0_Pos (0U)
4166 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4167 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4168 #define CAN_F1R2_FB1_Pos (1U)
4169 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4170 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4171 #define CAN_F1R2_FB2_Pos (2U)
4172 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4173 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4174 #define CAN_F1R2_FB3_Pos (3U)
4175 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4176 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4177 #define CAN_F1R2_FB4_Pos (4U)
4178 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4179 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4180 #define CAN_F1R2_FB5_Pos (5U)
4181 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4182 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4183 #define CAN_F1R2_FB6_Pos (6U)
4184 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4185 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4186 #define CAN_F1R2_FB7_Pos (7U)
4187 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4188 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4189 #define CAN_F1R2_FB8_Pos (8U)
4190 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4191 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4192 #define CAN_F1R2_FB9_Pos (9U)
4193 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4194 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4195 #define CAN_F1R2_FB10_Pos (10U)
4196 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4197 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4198 #define CAN_F1R2_FB11_Pos (11U)
4199 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4200 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4201 #define CAN_F1R2_FB12_Pos (12U)
4202 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4203 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4204 #define CAN_F1R2_FB13_Pos (13U)
4205 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4206 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4207 #define CAN_F1R2_FB14_Pos (14U)
4208 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4209 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4210 #define CAN_F1R2_FB15_Pos (15U)
4211 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4212 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4213 #define CAN_F1R2_FB16_Pos (16U)
4214 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4215 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4216 #define CAN_F1R2_FB17_Pos (17U)
4217 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4218 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4219 #define CAN_F1R2_FB18_Pos (18U)
4220 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4221 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4222 #define CAN_F1R2_FB19_Pos (19U)
4223 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4224 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4225 #define CAN_F1R2_FB20_Pos (20U)
4226 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4227 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4228 #define CAN_F1R2_FB21_Pos (21U)
4229 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4230 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4231 #define CAN_F1R2_FB22_Pos (22U)
4232 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4233 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4234 #define CAN_F1R2_FB23_Pos (23U)
4235 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4236 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4237 #define CAN_F1R2_FB24_Pos (24U)
4238 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4239 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4240 #define CAN_F1R2_FB25_Pos (25U)
4241 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4242 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4243 #define CAN_F1R2_FB26_Pos (26U)
4244 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4245 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4246 #define CAN_F1R2_FB27_Pos (27U)
4247 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4248 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4249 #define CAN_F1R2_FB28_Pos (28U)
4250 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4251 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4252 #define CAN_F1R2_FB29_Pos (29U)
4253 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4254 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4255 #define CAN_F1R2_FB30_Pos (30U)
4256 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4257 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4258 #define CAN_F1R2_FB31_Pos (31U)
4259 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4260 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4262 /******************* Bit definition for CAN_F2R2 register *******************/
4263 #define CAN_F2R2_FB0_Pos (0U)
4264 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4265 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4266 #define CAN_F2R2_FB1_Pos (1U)
4267 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4268 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4269 #define CAN_F2R2_FB2_Pos (2U)
4270 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4271 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4272 #define CAN_F2R2_FB3_Pos (3U)
4273 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4274 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4275 #define CAN_F2R2_FB4_Pos (4U)
4276 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4277 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4278 #define CAN_F2R2_FB5_Pos (5U)
4279 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4280 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4281 #define CAN_F2R2_FB6_Pos (6U)
4282 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4283 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4284 #define CAN_F2R2_FB7_Pos (7U)
4285 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4286 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4287 #define CAN_F2R2_FB8_Pos (8U)
4288 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4289 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4290 #define CAN_F2R2_FB9_Pos (9U)
4291 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4292 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4293 #define CAN_F2R2_FB10_Pos (10U)
4294 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4295 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4296 #define CAN_F2R2_FB11_Pos (11U)
4297 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4298 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4299 #define CAN_F2R2_FB12_Pos (12U)
4300 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4301 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4302 #define CAN_F2R2_FB13_Pos (13U)
4303 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4304 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4305 #define CAN_F2R2_FB14_Pos (14U)
4306 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4307 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4308 #define CAN_F2R2_FB15_Pos (15U)
4309 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4310 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4311 #define CAN_F2R2_FB16_Pos (16U)
4312 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4313 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4314 #define CAN_F2R2_FB17_Pos (17U)
4315 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4316 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4317 #define CAN_F2R2_FB18_Pos (18U)
4318 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4319 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4320 #define CAN_F2R2_FB19_Pos (19U)
4321 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4322 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4323 #define CAN_F2R2_FB20_Pos (20U)
4324 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4325 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4326 #define CAN_F2R2_FB21_Pos (21U)
4327 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4328 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4329 #define CAN_F2R2_FB22_Pos (22U)
4330 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4331 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4332 #define CAN_F2R2_FB23_Pos (23U)
4333 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4334 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4335 #define CAN_F2R2_FB24_Pos (24U)
4336 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4337 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4338 #define CAN_F2R2_FB25_Pos (25U)
4339 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4340 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4341 #define CAN_F2R2_FB26_Pos (26U)
4342 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4343 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4344 #define CAN_F2R2_FB27_Pos (27U)
4345 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4346 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4347 #define CAN_F2R2_FB28_Pos (28U)
4348 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4349 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4350 #define CAN_F2R2_FB29_Pos (29U)
4351 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4352 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4353 #define CAN_F2R2_FB30_Pos (30U)
4354 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4355 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4356 #define CAN_F2R2_FB31_Pos (31U)
4357 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4358 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4360 /******************* Bit definition for CAN_F3R2 register *******************/
4361 #define CAN_F3R2_FB0_Pos (0U)
4362 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4363 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4364 #define CAN_F3R2_FB1_Pos (1U)
4365 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4366 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4367 #define CAN_F3R2_FB2_Pos (2U)
4368 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4369 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4370 #define CAN_F3R2_FB3_Pos (3U)
4371 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4372 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4373 #define CAN_F3R2_FB4_Pos (4U)
4374 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4375 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4376 #define CAN_F3R2_FB5_Pos (5U)
4377 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4378 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4379 #define CAN_F3R2_FB6_Pos (6U)
4380 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4381 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4382 #define CAN_F3R2_FB7_Pos (7U)
4383 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4384 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4385 #define CAN_F3R2_FB8_Pos (8U)
4386 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4387 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4388 #define CAN_F3R2_FB9_Pos (9U)
4389 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4390 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4391 #define CAN_F3R2_FB10_Pos (10U)
4392 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4393 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4394 #define CAN_F3R2_FB11_Pos (11U)
4395 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4396 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4397 #define CAN_F3R2_FB12_Pos (12U)
4398 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4399 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4400 #define CAN_F3R2_FB13_Pos (13U)
4401 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4402 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4403 #define CAN_F3R2_FB14_Pos (14U)
4404 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4405 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4406 #define CAN_F3R2_FB15_Pos (15U)
4407 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4408 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4409 #define CAN_F3R2_FB16_Pos (16U)
4410 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4411 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4412 #define CAN_F3R2_FB17_Pos (17U)
4413 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4414 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4415 #define CAN_F3R2_FB18_Pos (18U)
4416 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4417 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4418 #define CAN_F3R2_FB19_Pos (19U)
4419 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4420 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4421 #define CAN_F3R2_FB20_Pos (20U)
4422 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4423 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4424 #define CAN_F3R2_FB21_Pos (21U)
4425 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4426 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4427 #define CAN_F3R2_FB22_Pos (22U)
4428 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4429 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4430 #define CAN_F3R2_FB23_Pos (23U)
4431 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4432 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4433 #define CAN_F3R2_FB24_Pos (24U)
4434 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4435 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4436 #define CAN_F3R2_FB25_Pos (25U)
4437 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4438 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4439 #define CAN_F3R2_FB26_Pos (26U)
4440 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4441 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4442 #define CAN_F3R2_FB27_Pos (27U)
4443 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4444 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4445 #define CAN_F3R2_FB28_Pos (28U)
4446 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4447 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4448 #define CAN_F3R2_FB29_Pos (29U)
4449 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4450 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4451 #define CAN_F3R2_FB30_Pos (30U)
4452 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4453 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4454 #define CAN_F3R2_FB31_Pos (31U)
4455 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4456 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4458 /******************* Bit definition for CAN_F4R2 register *******************/
4459 #define CAN_F4R2_FB0_Pos (0U)
4460 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4461 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4462 #define CAN_F4R2_FB1_Pos (1U)
4463 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4464 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4465 #define CAN_F4R2_FB2_Pos (2U)
4466 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4467 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4468 #define CAN_F4R2_FB3_Pos (3U)
4469 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4470 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4471 #define CAN_F4R2_FB4_Pos (4U)
4472 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4473 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4474 #define CAN_F4R2_FB5_Pos (5U)
4475 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4476 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4477 #define CAN_F4R2_FB6_Pos (6U)
4478 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4479 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4480 #define CAN_F4R2_FB7_Pos (7U)
4481 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4482 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4483 #define CAN_F4R2_FB8_Pos (8U)
4484 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4485 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4486 #define CAN_F4R2_FB9_Pos (9U)
4487 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4488 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4489 #define CAN_F4R2_FB10_Pos (10U)
4490 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4491 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4492 #define CAN_F4R2_FB11_Pos (11U)
4493 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4494 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4495 #define CAN_F4R2_FB12_Pos (12U)
4496 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4497 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4498 #define CAN_F4R2_FB13_Pos (13U)
4499 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4500 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4501 #define CAN_F4R2_FB14_Pos (14U)
4502 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4503 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4504 #define CAN_F4R2_FB15_Pos (15U)
4505 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4506 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4507 #define CAN_F4R2_FB16_Pos (16U)
4508 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4509 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4510 #define CAN_F4R2_FB17_Pos (17U)
4511 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4512 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4513 #define CAN_F4R2_FB18_Pos (18U)
4514 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4515 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4516 #define CAN_F4R2_FB19_Pos (19U)
4517 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4518 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4519 #define CAN_F4R2_FB20_Pos (20U)
4520 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4521 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4522 #define CAN_F4R2_FB21_Pos (21U)
4523 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4524 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4525 #define CAN_F4R2_FB22_Pos (22U)
4526 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4527 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4528 #define CAN_F4R2_FB23_Pos (23U)
4529 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4530 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4531 #define CAN_F4R2_FB24_Pos (24U)
4532 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4533 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4534 #define CAN_F4R2_FB25_Pos (25U)
4535 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4536 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4537 #define CAN_F4R2_FB26_Pos (26U)
4538 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4539 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4540 #define CAN_F4R2_FB27_Pos (27U)
4541 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4542 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4543 #define CAN_F4R2_FB28_Pos (28U)
4544 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4545 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4546 #define CAN_F4R2_FB29_Pos (29U)
4547 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4548 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4549 #define CAN_F4R2_FB30_Pos (30U)
4550 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4551 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4552 #define CAN_F4R2_FB31_Pos (31U)
4553 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4554 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4556 /******************* Bit definition for CAN_F5R2 register *******************/
4557 #define CAN_F5R2_FB0_Pos (0U)
4558 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4559 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4560 #define CAN_F5R2_FB1_Pos (1U)
4561 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4562 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4563 #define CAN_F5R2_FB2_Pos (2U)
4564 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4565 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4566 #define CAN_F5R2_FB3_Pos (3U)
4567 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4568 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4569 #define CAN_F5R2_FB4_Pos (4U)
4570 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4571 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4572 #define CAN_F5R2_FB5_Pos (5U)
4573 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4574 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4575 #define CAN_F5R2_FB6_Pos (6U)
4576 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4577 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4578 #define CAN_F5R2_FB7_Pos (7U)
4579 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4580 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4581 #define CAN_F5R2_FB8_Pos (8U)
4582 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4583 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4584 #define CAN_F5R2_FB9_Pos (9U)
4585 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4586 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4587 #define CAN_F5R2_FB10_Pos (10U)
4588 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4589 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4590 #define CAN_F5R2_FB11_Pos (11U)
4591 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4592 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4593 #define CAN_F5R2_FB12_Pos (12U)
4594 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4595 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4596 #define CAN_F5R2_FB13_Pos (13U)
4597 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4598 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4599 #define CAN_F5R2_FB14_Pos (14U)
4600 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4601 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4602 #define CAN_F5R2_FB15_Pos (15U)
4603 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4604 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4605 #define CAN_F5R2_FB16_Pos (16U)
4606 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4607 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4608 #define CAN_F5R2_FB17_Pos (17U)
4609 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4610 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4611 #define CAN_F5R2_FB18_Pos (18U)
4612 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4613 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4614 #define CAN_F5R2_FB19_Pos (19U)
4615 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4616 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4617 #define CAN_F5R2_FB20_Pos (20U)
4618 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4619 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4620 #define CAN_F5R2_FB21_Pos (21U)
4621 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4622 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4623 #define CAN_F5R2_FB22_Pos (22U)
4624 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4625 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4626 #define CAN_F5R2_FB23_Pos (23U)
4627 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4628 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4629 #define CAN_F5R2_FB24_Pos (24U)
4630 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4631 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4632 #define CAN_F5R2_FB25_Pos (25U)
4633 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4634 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4635 #define CAN_F5R2_FB26_Pos (26U)
4636 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4637 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4638 #define CAN_F5R2_FB27_Pos (27U)
4639 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4640 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4641 #define CAN_F5R2_FB28_Pos (28U)
4642 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4643 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4644 #define CAN_F5R2_FB29_Pos (29U)
4645 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4646 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4647 #define CAN_F5R2_FB30_Pos (30U)
4648 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4649 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4650 #define CAN_F5R2_FB31_Pos (31U)
4651 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4652 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4654 /******************* Bit definition for CAN_F6R2 register *******************/
4655 #define CAN_F6R2_FB0_Pos (0U)
4656 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4657 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4658 #define CAN_F6R2_FB1_Pos (1U)
4659 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4660 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4661 #define CAN_F6R2_FB2_Pos (2U)
4662 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4663 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4664 #define CAN_F6R2_FB3_Pos (3U)
4665 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4666 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4667 #define CAN_F6R2_FB4_Pos (4U)
4668 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4669 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4670 #define CAN_F6R2_FB5_Pos (5U)
4671 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4672 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4673 #define CAN_F6R2_FB6_Pos (6U)
4674 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4675 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4676 #define CAN_F6R2_FB7_Pos (7U)
4677 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4678 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4679 #define CAN_F6R2_FB8_Pos (8U)
4680 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4681 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4682 #define CAN_F6R2_FB9_Pos (9U)
4683 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4684 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4685 #define CAN_F6R2_FB10_Pos (10U)
4686 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4687 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4688 #define CAN_F6R2_FB11_Pos (11U)
4689 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4690 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4691 #define CAN_F6R2_FB12_Pos (12U)
4692 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4693 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4694 #define CAN_F6R2_FB13_Pos (13U)
4695 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4696 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4697 #define CAN_F6R2_FB14_Pos (14U)
4698 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4699 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4700 #define CAN_F6R2_FB15_Pos (15U)
4701 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4702 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4703 #define CAN_F6R2_FB16_Pos (16U)
4704 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4705 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4706 #define CAN_F6R2_FB17_Pos (17U)
4707 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4708 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4709 #define CAN_F6R2_FB18_Pos (18U)
4710 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4711 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4712 #define CAN_F6R2_FB19_Pos (19U)
4713 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4714 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4715 #define CAN_F6R2_FB20_Pos (20U)
4716 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4717 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4718 #define CAN_F6R2_FB21_Pos (21U)
4719 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4720 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4721 #define CAN_F6R2_FB22_Pos (22U)
4722 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4723 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4724 #define CAN_F6R2_FB23_Pos (23U)
4725 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4726 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4727 #define CAN_F6R2_FB24_Pos (24U)
4728 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4729 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4730 #define CAN_F6R2_FB25_Pos (25U)
4731 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4732 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4733 #define CAN_F6R2_FB26_Pos (26U)
4734 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4735 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4736 #define CAN_F6R2_FB27_Pos (27U)
4737 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4738 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4739 #define CAN_F6R2_FB28_Pos (28U)
4740 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4741 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4742 #define CAN_F6R2_FB29_Pos (29U)
4743 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4744 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4745 #define CAN_F6R2_FB30_Pos (30U)
4746 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4747 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4748 #define CAN_F6R2_FB31_Pos (31U)
4749 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4750 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4752 /******************* Bit definition for CAN_F7R2 register *******************/
4753 #define CAN_F7R2_FB0_Pos (0U)
4754 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4755 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4756 #define CAN_F7R2_FB1_Pos (1U)
4757 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4758 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4759 #define CAN_F7R2_FB2_Pos (2U)
4760 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4761 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4762 #define CAN_F7R2_FB3_Pos (3U)
4763 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4764 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4765 #define CAN_F7R2_FB4_Pos (4U)
4766 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4767 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4768 #define CAN_F7R2_FB5_Pos (5U)
4769 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4770 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4771 #define CAN_F7R2_FB6_Pos (6U)
4772 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4773 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4774 #define CAN_F7R2_FB7_Pos (7U)
4775 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4776 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4777 #define CAN_F7R2_FB8_Pos (8U)
4778 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4779 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4780 #define CAN_F7R2_FB9_Pos (9U)
4781 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4782 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4783 #define CAN_F7R2_FB10_Pos (10U)
4784 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4785 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4786 #define CAN_F7R2_FB11_Pos (11U)
4787 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4788 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4789 #define CAN_F7R2_FB12_Pos (12U)
4790 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4791 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4792 #define CAN_F7R2_FB13_Pos (13U)
4793 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4794 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4795 #define CAN_F7R2_FB14_Pos (14U)
4796 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4797 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4798 #define CAN_F7R2_FB15_Pos (15U)
4799 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4800 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4801 #define CAN_F7R2_FB16_Pos (16U)
4802 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4803 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4804 #define CAN_F7R2_FB17_Pos (17U)
4805 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4806 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4807 #define CAN_F7R2_FB18_Pos (18U)
4808 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4809 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4810 #define CAN_F7R2_FB19_Pos (19U)
4811 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4812 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4813 #define CAN_F7R2_FB20_Pos (20U)
4814 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4815 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4816 #define CAN_F7R2_FB21_Pos (21U)
4817 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4818 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4819 #define CAN_F7R2_FB22_Pos (22U)
4820 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4821 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4822 #define CAN_F7R2_FB23_Pos (23U)
4823 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4824 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4825 #define CAN_F7R2_FB24_Pos (24U)
4826 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4827 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4828 #define CAN_F7R2_FB25_Pos (25U)
4829 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4830 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4831 #define CAN_F7R2_FB26_Pos (26U)
4832 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4833 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4834 #define CAN_F7R2_FB27_Pos (27U)
4835 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4836 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4837 #define CAN_F7R2_FB28_Pos (28U)
4838 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4839 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4840 #define CAN_F7R2_FB29_Pos (29U)
4841 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4842 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4843 #define CAN_F7R2_FB30_Pos (30U)
4844 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4845 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4846 #define CAN_F7R2_FB31_Pos (31U)
4847 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4848 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4850 /******************* Bit definition for CAN_F8R2 register *******************/
4851 #define CAN_F8R2_FB0_Pos (0U)
4852 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4853 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4854 #define CAN_F8R2_FB1_Pos (1U)
4855 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4856 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4857 #define CAN_F8R2_FB2_Pos (2U)
4858 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4859 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4860 #define CAN_F8R2_FB3_Pos (3U)
4861 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4862 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4863 #define CAN_F8R2_FB4_Pos (4U)
4864 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4865 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4866 #define CAN_F8R2_FB5_Pos (5U)
4867 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4868 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4869 #define CAN_F8R2_FB6_Pos (6U)
4870 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4871 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4872 #define CAN_F8R2_FB7_Pos (7U)
4873 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4874 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4875 #define CAN_F8R2_FB8_Pos (8U)
4876 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4877 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4878 #define CAN_F8R2_FB9_Pos (9U)
4879 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4880 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4881 #define CAN_F8R2_FB10_Pos (10U)
4882 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4883 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4884 #define CAN_F8R2_FB11_Pos (11U)
4885 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4886 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4887 #define CAN_F8R2_FB12_Pos (12U)
4888 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4889 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4890 #define CAN_F8R2_FB13_Pos (13U)
4891 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4892 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4893 #define CAN_F8R2_FB14_Pos (14U)
4894 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4895 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4896 #define CAN_F8R2_FB15_Pos (15U)
4897 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4898 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4899 #define CAN_F8R2_FB16_Pos (16U)
4900 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4901 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4902 #define CAN_F8R2_FB17_Pos (17U)
4903 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4904 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4905 #define CAN_F8R2_FB18_Pos (18U)
4906 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4907 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4908 #define CAN_F8R2_FB19_Pos (19U)
4909 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4910 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4911 #define CAN_F8R2_FB20_Pos (20U)
4912 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4913 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4914 #define CAN_F8R2_FB21_Pos (21U)
4915 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4916 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4917 #define CAN_F8R2_FB22_Pos (22U)
4918 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4919 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4920 #define CAN_F8R2_FB23_Pos (23U)
4921 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4922 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4923 #define CAN_F8R2_FB24_Pos (24U)
4924 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4925 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4926 #define CAN_F8R2_FB25_Pos (25U)
4927 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4928 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4929 #define CAN_F8R2_FB26_Pos (26U)
4930 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4931 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4932 #define CAN_F8R2_FB27_Pos (27U)
4933 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4934 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4935 #define CAN_F8R2_FB28_Pos (28U)
4936 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4937 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4938 #define CAN_F8R2_FB29_Pos (29U)
4939 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4940 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4941 #define CAN_F8R2_FB30_Pos (30U)
4942 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4943 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4944 #define CAN_F8R2_FB31_Pos (31U)
4945 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4946 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4948 /******************* Bit definition for CAN_F9R2 register *******************/
4949 #define CAN_F9R2_FB0_Pos (0U)
4950 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4951 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4952 #define CAN_F9R2_FB1_Pos (1U)
4953 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4954 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4955 #define CAN_F9R2_FB2_Pos (2U)
4956 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4957 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4958 #define CAN_F9R2_FB3_Pos (3U)
4959 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4960 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4961 #define CAN_F9R2_FB4_Pos (4U)
4962 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4963 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4964 #define CAN_F9R2_FB5_Pos (5U)
4965 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4966 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4967 #define CAN_F9R2_FB6_Pos (6U)
4968 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4969 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4970 #define CAN_F9R2_FB7_Pos (7U)
4971 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4972 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4973 #define CAN_F9R2_FB8_Pos (8U)
4974 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4975 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4976 #define CAN_F9R2_FB9_Pos (9U)
4977 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4978 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4979 #define CAN_F9R2_FB10_Pos (10U)
4980 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4981 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4982 #define CAN_F9R2_FB11_Pos (11U)
4983 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4984 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4985 #define CAN_F9R2_FB12_Pos (12U)
4986 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4987 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4988 #define CAN_F9R2_FB13_Pos (13U)
4989 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4990 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4991 #define CAN_F9R2_FB14_Pos (14U)
4992 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4993 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4994 #define CAN_F9R2_FB15_Pos (15U)
4995 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4996 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4997 #define CAN_F9R2_FB16_Pos (16U)
4998 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4999 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5000 #define CAN_F9R2_FB17_Pos (17U)
5001 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5002 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5003 #define CAN_F9R2_FB18_Pos (18U)
5004 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5005 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5006 #define CAN_F9R2_FB19_Pos (19U)
5007 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5008 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5009 #define CAN_F9R2_FB20_Pos (20U)
5010 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5011 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5012 #define CAN_F9R2_FB21_Pos (21U)
5013 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5014 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5015 #define CAN_F9R2_FB22_Pos (22U)
5016 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5017 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5018 #define CAN_F9R2_FB23_Pos (23U)
5019 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5020 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5021 #define CAN_F9R2_FB24_Pos (24U)
5022 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5023 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5024 #define CAN_F9R2_FB25_Pos (25U)
5025 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5026 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5027 #define CAN_F9R2_FB26_Pos (26U)
5028 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5029 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5030 #define CAN_F9R2_FB27_Pos (27U)
5031 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5032 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5033 #define CAN_F9R2_FB28_Pos (28U)
5034 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5035 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5036 #define CAN_F9R2_FB29_Pos (29U)
5037 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5038 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5039 #define CAN_F9R2_FB30_Pos (30U)
5040 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5041 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5042 #define CAN_F9R2_FB31_Pos (31U)
5043 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5044 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5046 /******************* Bit definition for CAN_F10R2 register ******************/
5047 #define CAN_F10R2_FB0_Pos (0U)
5048 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5049 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5050 #define CAN_F10R2_FB1_Pos (1U)
5051 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5052 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5053 #define CAN_F10R2_FB2_Pos (2U)
5054 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5055 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5056 #define CAN_F10R2_FB3_Pos (3U)
5057 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5058 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5059 #define CAN_F10R2_FB4_Pos (4U)
5060 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5061 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5062 #define CAN_F10R2_FB5_Pos (5U)
5063 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5064 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5065 #define CAN_F10R2_FB6_Pos (6U)
5066 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5067 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5068 #define CAN_F10R2_FB7_Pos (7U)
5069 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5070 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5071 #define CAN_F10R2_FB8_Pos (8U)
5072 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5073 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5074 #define CAN_F10R2_FB9_Pos (9U)
5075 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5076 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5077 #define CAN_F10R2_FB10_Pos (10U)
5078 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5079 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5080 #define CAN_F10R2_FB11_Pos (11U)
5081 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5082 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5083 #define CAN_F10R2_FB12_Pos (12U)
5084 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5085 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5086 #define CAN_F10R2_FB13_Pos (13U)
5087 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5088 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5089 #define CAN_F10R2_FB14_Pos (14U)
5090 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5091 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5092 #define CAN_F10R2_FB15_Pos (15U)
5093 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5094 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5095 #define CAN_F10R2_FB16_Pos (16U)
5096 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5097 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5098 #define CAN_F10R2_FB17_Pos (17U)
5099 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5100 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5101 #define CAN_F10R2_FB18_Pos (18U)
5102 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5103 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5104 #define CAN_F10R2_FB19_Pos (19U)
5105 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5106 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5107 #define CAN_F10R2_FB20_Pos (20U)
5108 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5109 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5110 #define CAN_F10R2_FB21_Pos (21U)
5111 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5112 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5113 #define CAN_F10R2_FB22_Pos (22U)
5114 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5115 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5116 #define CAN_F10R2_FB23_Pos (23U)
5117 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5118 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5119 #define CAN_F10R2_FB24_Pos (24U)
5120 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5121 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5122 #define CAN_F10R2_FB25_Pos (25U)
5123 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5124 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5125 #define CAN_F10R2_FB26_Pos (26U)
5126 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5127 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5128 #define CAN_F10R2_FB27_Pos (27U)
5129 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5130 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5131 #define CAN_F10R2_FB28_Pos (28U)
5132 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5133 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5134 #define CAN_F10R2_FB29_Pos (29U)
5135 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5136 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5137 #define CAN_F10R2_FB30_Pos (30U)
5138 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5139 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5140 #define CAN_F10R2_FB31_Pos (31U)
5141 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5142 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5144 /******************* Bit definition for CAN_F11R2 register ******************/
5145 #define CAN_F11R2_FB0_Pos (0U)
5146 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5147 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5148 #define CAN_F11R2_FB1_Pos (1U)
5149 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5150 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5151 #define CAN_F11R2_FB2_Pos (2U)
5152 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5153 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5154 #define CAN_F11R2_FB3_Pos (3U)
5155 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5156 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5157 #define CAN_F11R2_FB4_Pos (4U)
5158 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5159 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5160 #define CAN_F11R2_FB5_Pos (5U)
5161 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5162 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5163 #define CAN_F11R2_FB6_Pos (6U)
5164 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5165 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5166 #define CAN_F11R2_FB7_Pos (7U)
5167 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5168 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5169 #define CAN_F11R2_FB8_Pos (8U)
5170 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5171 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5172 #define CAN_F11R2_FB9_Pos (9U)
5173 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5174 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5175 #define CAN_F11R2_FB10_Pos (10U)
5176 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5177 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5178 #define CAN_F11R2_FB11_Pos (11U)
5179 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5180 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5181 #define CAN_F11R2_FB12_Pos (12U)
5182 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5183 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5184 #define CAN_F11R2_FB13_Pos (13U)
5185 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5186 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5187 #define CAN_F11R2_FB14_Pos (14U)
5188 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5189 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5190 #define CAN_F11R2_FB15_Pos (15U)
5191 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5192 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5193 #define CAN_F11R2_FB16_Pos (16U)
5194 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5195 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5196 #define CAN_F11R2_FB17_Pos (17U)
5197 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5198 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5199 #define CAN_F11R2_FB18_Pos (18U)
5200 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5201 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5202 #define CAN_F11R2_FB19_Pos (19U)
5203 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5204 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5205 #define CAN_F11R2_FB20_Pos (20U)
5206 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5207 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5208 #define CAN_F11R2_FB21_Pos (21U)
5209 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5210 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5211 #define CAN_F11R2_FB22_Pos (22U)
5212 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5213 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5214 #define CAN_F11R2_FB23_Pos (23U)
5215 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5216 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5217 #define CAN_F11R2_FB24_Pos (24U)
5218 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5219 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5220 #define CAN_F11R2_FB25_Pos (25U)
5221 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5222 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5223 #define CAN_F11R2_FB26_Pos (26U)
5224 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5225 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5226 #define CAN_F11R2_FB27_Pos (27U)
5227 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5228 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5229 #define CAN_F11R2_FB28_Pos (28U)
5230 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5231 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5232 #define CAN_F11R2_FB29_Pos (29U)
5233 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5234 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5235 #define CAN_F11R2_FB30_Pos (30U)
5236 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5237 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5238 #define CAN_F11R2_FB31_Pos (31U)
5239 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5240 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5242 /******************* Bit definition for CAN_F12R2 register ******************/
5243 #define CAN_F12R2_FB0_Pos (0U)
5244 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5245 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5246 #define CAN_F12R2_FB1_Pos (1U)
5247 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5248 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5249 #define CAN_F12R2_FB2_Pos (2U)
5250 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5251 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5252 #define CAN_F12R2_FB3_Pos (3U)
5253 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5254 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5255 #define CAN_F12R2_FB4_Pos (4U)
5256 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5257 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5258 #define CAN_F12R2_FB5_Pos (5U)
5259 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5260 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5261 #define CAN_F12R2_FB6_Pos (6U)
5262 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5263 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5264 #define CAN_F12R2_FB7_Pos (7U)
5265 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5266 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5267 #define CAN_F12R2_FB8_Pos (8U)
5268 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5269 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5270 #define CAN_F12R2_FB9_Pos (9U)
5271 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5272 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5273 #define CAN_F12R2_FB10_Pos (10U)
5274 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5275 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5276 #define CAN_F12R2_FB11_Pos (11U)
5277 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5278 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5279 #define CAN_F12R2_FB12_Pos (12U)
5280 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5281 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5282 #define CAN_F12R2_FB13_Pos (13U)
5283 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5284 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5285 #define CAN_F12R2_FB14_Pos (14U)
5286 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5287 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5288 #define CAN_F12R2_FB15_Pos (15U)
5289 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5290 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5291 #define CAN_F12R2_FB16_Pos (16U)
5292 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5293 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5294 #define CAN_F12R2_FB17_Pos (17U)
5295 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5296 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5297 #define CAN_F12R2_FB18_Pos (18U)
5298 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5299 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5300 #define CAN_F12R2_FB19_Pos (19U)
5301 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5302 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5303 #define CAN_F12R2_FB20_Pos (20U)
5304 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5305 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5306 #define CAN_F12R2_FB21_Pos (21U)
5307 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5308 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5309 #define CAN_F12R2_FB22_Pos (22U)
5310 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5311 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5312 #define CAN_F12R2_FB23_Pos (23U)
5313 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5314 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5315 #define CAN_F12R2_FB24_Pos (24U)
5316 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5317 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5318 #define CAN_F12R2_FB25_Pos (25U)
5319 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5320 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5321 #define CAN_F12R2_FB26_Pos (26U)
5322 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5323 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5324 #define CAN_F12R2_FB27_Pos (27U)
5325 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5326 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5327 #define CAN_F12R2_FB28_Pos (28U)
5328 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5329 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5330 #define CAN_F12R2_FB29_Pos (29U)
5331 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5332 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5333 #define CAN_F12R2_FB30_Pos (30U)
5334 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5335 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5336 #define CAN_F12R2_FB31_Pos (31U)
5337 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5338 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5340 /******************* Bit definition for CAN_F13R2 register ******************/
5341 #define CAN_F13R2_FB0_Pos (0U)
5342 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5343 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5344 #define CAN_F13R2_FB1_Pos (1U)
5345 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5346 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5347 #define CAN_F13R2_FB2_Pos (2U)
5348 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5349 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5350 #define CAN_F13R2_FB3_Pos (3U)
5351 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5352 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5353 #define CAN_F13R2_FB4_Pos (4U)
5354 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5355 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5356 #define CAN_F13R2_FB5_Pos (5U)
5357 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5358 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5359 #define CAN_F13R2_FB6_Pos (6U)
5360 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5361 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5362 #define CAN_F13R2_FB7_Pos (7U)
5363 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5364 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5365 #define CAN_F13R2_FB8_Pos (8U)
5366 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5367 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5368 #define CAN_F13R2_FB9_Pos (9U)
5369 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5370 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5371 #define CAN_F13R2_FB10_Pos (10U)
5372 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5373 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5374 #define CAN_F13R2_FB11_Pos (11U)
5375 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5376 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5377 #define CAN_F13R2_FB12_Pos (12U)
5378 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5379 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5380 #define CAN_F13R2_FB13_Pos (13U)
5381 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5382 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5383 #define CAN_F13R2_FB14_Pos (14U)
5384 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5385 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5386 #define CAN_F13R2_FB15_Pos (15U)
5387 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5388 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5389 #define CAN_F13R2_FB16_Pos (16U)
5390 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5391 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5392 #define CAN_F13R2_FB17_Pos (17U)
5393 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5394 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5395 #define CAN_F13R2_FB18_Pos (18U)
5396 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5397 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5398 #define CAN_F13R2_FB19_Pos (19U)
5399 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5400 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5401 #define CAN_F13R2_FB20_Pos (20U)
5402 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5403 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5404 #define CAN_F13R2_FB21_Pos (21U)
5405 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5406 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5407 #define CAN_F13R2_FB22_Pos (22U)
5408 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5409 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5410 #define CAN_F13R2_FB23_Pos (23U)
5411 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5412 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5413 #define CAN_F13R2_FB24_Pos (24U)
5414 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5415 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5416 #define CAN_F13R2_FB25_Pos (25U)
5417 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5418 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5419 #define CAN_F13R2_FB26_Pos (26U)
5420 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5421 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5422 #define CAN_F13R2_FB27_Pos (27U)
5423 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5424 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5425 #define CAN_F13R2_FB28_Pos (28U)
5426 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5427 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5428 #define CAN_F13R2_FB29_Pos (29U)
5429 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5430 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5431 #define CAN_F13R2_FB30_Pos (30U)
5432 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5433 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5434 #define CAN_F13R2_FB31_Pos (31U)
5435 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5436 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5438 /******************************************************************************/
5439 /* */
5440 /* HDMI-CEC (CEC) */
5441 /* */
5442 /******************************************************************************/
5443 
5444 /******************* Bit definition for CEC_CR register *********************/
5445 #define CEC_CR_CECEN_Pos (0U)
5446 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5447 #define CEC_CR_CECEN CEC_CR_CECEN_Msk
5448 #define CEC_CR_TXSOM_Pos (1U)
5449 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5450 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5451 #define CEC_CR_TXEOM_Pos (2U)
5452 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5453 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5455 /******************* Bit definition for CEC_CFGR register *******************/
5456 #define CEC_CFGR_SFT_Pos (0U)
5457 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5458 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5459 #define CEC_CFGR_RXTOL_Pos (3U)
5460 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5461 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5462 #define CEC_CFGR_BRESTP_Pos (4U)
5463 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5464 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5465 #define CEC_CFGR_BREGEN_Pos (5U)
5466 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5467 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5468 #define CEC_CFGR_LBPEGEN_Pos (6U)
5469 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5470 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5471 #define CEC_CFGR_SFTOPT_Pos (8U)
5472 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5473 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5474 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5475 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5476 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5477 #define CEC_CFGR_OAR_Pos (16U)
5478 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5479 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5480 #define CEC_CFGR_LSTN_Pos (31U)
5481 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5482 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5484 /******************* Bit definition for CEC_TXDR register *******************/
5485 #define CEC_TXDR_TXD_Pos (0U)
5486 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5487 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5489 /******************* Bit definition for CEC_RXDR register *******************/
5490 #define CEC_RXDR_RXD_Pos (0U)
5491 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5492 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5493 /*legacy define*/
5494 #define CEC_TXDR_RXD CEC_RXDR_RXD
5496 /******************* Bit definition for CEC_ISR register ********************/
5497 #define CEC_ISR_RXBR_Pos (0U)
5498 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5499 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5500 #define CEC_ISR_RXEND_Pos (1U)
5501 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5502 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5503 #define CEC_ISR_RXOVR_Pos (2U)
5504 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5505 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5506 #define CEC_ISR_BRE_Pos (3U)
5507 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5508 #define CEC_ISR_BRE CEC_ISR_BRE_Msk
5509 #define CEC_ISR_SBPE_Pos (4U)
5510 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5511 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5512 #define CEC_ISR_LBPE_Pos (5U)
5513 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5514 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5515 #define CEC_ISR_RXACKE_Pos (6U)
5516 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5517 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5518 #define CEC_ISR_ARBLST_Pos (7U)
5519 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5520 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5521 #define CEC_ISR_TXBR_Pos (8U)
5522 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5523 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5524 #define CEC_ISR_TXEND_Pos (9U)
5525 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5526 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5527 #define CEC_ISR_TXUDR_Pos (10U)
5528 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5529 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5530 #define CEC_ISR_TXERR_Pos (11U)
5531 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5532 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5533 #define CEC_ISR_TXACKE_Pos (12U)
5534 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5535 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5537 /******************* Bit definition for CEC_IER register ********************/
5538 #define CEC_IER_RXBRIE_Pos (0U)
5539 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5540 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5541 #define CEC_IER_RXENDIE_Pos (1U)
5542 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5543 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5544 #define CEC_IER_RXOVRIE_Pos (2U)
5545 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5546 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5547 #define CEC_IER_BREIE_Pos (3U)
5548 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5549 #define CEC_IER_BREIE CEC_IER_BREIE_Msk
5550 #define CEC_IER_SBPEIE_Pos (4U)
5551 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5552 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5553 #define CEC_IER_LBPEIE_Pos (5U)
5554 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5555 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5556 #define CEC_IER_RXACKEIE_Pos (6U)
5557 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5558 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5559 #define CEC_IER_ARBLSTIE_Pos (7U)
5560 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5561 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5562 #define CEC_IER_TXBRIE_Pos (8U)
5563 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5564 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5565 #define CEC_IER_TXENDIE_Pos (9U)
5566 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5567 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5568 #define CEC_IER_TXUDRIE_Pos (10U)
5569 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5570 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5571 #define CEC_IER_TXERRIE_Pos (11U)
5572 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5573 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5574 #define CEC_IER_TXACKEIE_Pos (12U)
5575 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5576 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5578 /******************************************************************************/
5579 /* */
5580 /* CRC calculation unit */
5581 /* */
5582 /******************************************************************************/
5583 /******************* Bit definition for CRC_DR register *********************/
5584 #define CRC_DR_DR_Pos (0U)
5585 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5586 #define CRC_DR_DR CRC_DR_DR_Msk
5589 /******************* Bit definition for CRC_IDR register ********************/
5590 #define CRC_IDR_IDR_Pos (0U)
5591 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5592 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
5595 /******************** Bit definition for CRC_CR register ********************/
5596 #define CRC_CR_RESET_Pos (0U)
5597 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5598 #define CRC_CR_RESET CRC_CR_RESET_Msk
5600 /******************************************************************************/
5601 /* */
5602 /* Digital to Analog Converter */
5603 /* */
5604 /******************************************************************************/
5605 /*
5606  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5607  */
5608 #define DAC_CHANNEL2_SUPPORT
5609 /******************** Bit definition for DAC_CR register ********************/
5610 #define DAC_CR_EN1_Pos (0U)
5611 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5612 #define DAC_CR_EN1 DAC_CR_EN1_Msk
5613 #define DAC_CR_BOFF1_Pos (1U)
5614 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5615 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5616 #define DAC_CR_TEN1_Pos (2U)
5617 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5618 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5620 #define DAC_CR_TSEL1_Pos (3U)
5621 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5622 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5623 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5624 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5625 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5627 #define DAC_CR_WAVE1_Pos (6U)
5628 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5629 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5630 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5631 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5633 #define DAC_CR_MAMP1_Pos (8U)
5634 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5635 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5636 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5637 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5638 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5639 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5641 #define DAC_CR_DMAEN1_Pos (12U)
5642 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5643 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5644 #define DAC_CR_DMAUDRIE1_Pos (13U)
5645 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5646 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5647 #define DAC_CR_EN2_Pos (16U)
5648 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5649 #define DAC_CR_EN2 DAC_CR_EN2_Msk
5650 #define DAC_CR_BOFF2_Pos (17U)
5651 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5652 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5653 #define DAC_CR_TEN2_Pos (18U)
5654 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5655 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5657 #define DAC_CR_TSEL2_Pos (19U)
5658 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5659 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5660 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5661 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5662 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5664 #define DAC_CR_WAVE2_Pos (22U)
5665 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5666 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5667 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5668 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5670 #define DAC_CR_MAMP2_Pos (24U)
5671 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5672 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5673 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5674 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5675 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5676 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5678 #define DAC_CR_DMAEN2_Pos (28U)
5679 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5680 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5681 #define DAC_CR_DMAUDRIE2_Pos (29U)
5682 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5683 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5685 /***************** Bit definition for DAC_SWTRIGR register ******************/
5686 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5687 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5688 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5689 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5690 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5691 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5693 /***************** Bit definition for DAC_DHR12R1 register ******************/
5694 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5695 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5696 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5698 /***************** Bit definition for DAC_DHR12L1 register ******************/
5699 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5700 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5701 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5703 /****************** Bit definition for DAC_DHR8R1 register ******************/
5704 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5705 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5706 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5708 /***************** Bit definition for DAC_DHR12R2 register ******************/
5709 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5710 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5711 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5713 /***************** Bit definition for DAC_DHR12L2 register ******************/
5714 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5715 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5716 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5718 /****************** Bit definition for DAC_DHR8R2 register ******************/
5719 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5720 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5721 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5723 /***************** Bit definition for DAC_DHR12RD register ******************/
5724 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5725 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5726 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5727 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5728 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5729 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5731 /***************** Bit definition for DAC_DHR12LD register ******************/
5732 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5733 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5734 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5735 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5736 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5737 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5739 /****************** Bit definition for DAC_DHR8RD register ******************/
5740 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5741 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5742 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5743 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5744 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5745 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5747 /******************* Bit definition for DAC_DOR1 register *******************/
5748 #define DAC_DOR1_DACC1DOR_Pos (0U)
5749 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5750 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5752 /******************* Bit definition for DAC_DOR2 register *******************/
5753 #define DAC_DOR2_DACC2DOR_Pos (0U)
5754 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5755 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5757 /******************** Bit definition for DAC_SR register ********************/
5758 #define DAC_SR_DMAUDR1_Pos (13U)
5759 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5760 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5761 #define DAC_SR_DMAUDR2_Pos (29U)
5762 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5763 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5765 /******************************************************************************/
5766 /* */
5767 /* DCMI */
5768 /* */
5769 /******************************************************************************/
5770 /******************** Bits definition for DCMI_CR register ******************/
5771 #define DCMI_CR_CAPTURE_Pos (0U)
5772 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5773 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5774 #define DCMI_CR_CM_Pos (1U)
5775 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5776 #define DCMI_CR_CM DCMI_CR_CM_Msk
5777 #define DCMI_CR_CROP_Pos (2U)
5778 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5779 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5780 #define DCMI_CR_JPEG_Pos (3U)
5781 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5782 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5783 #define DCMI_CR_ESS_Pos (4U)
5784 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5785 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5786 #define DCMI_CR_PCKPOL_Pos (5U)
5787 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5788 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5789 #define DCMI_CR_HSPOL_Pos (6U)
5790 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5791 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5792 #define DCMI_CR_VSPOL_Pos (7U)
5793 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5794 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5795 #define DCMI_CR_FCRC_0 0x00000100U
5796 #define DCMI_CR_FCRC_1 0x00000200U
5797 #define DCMI_CR_EDM_0 0x00000400U
5798 #define DCMI_CR_EDM_1 0x00000800U
5799 #define DCMI_CR_OUTEN_Pos (13U)
5800 #define DCMI_CR_OUTEN_Msk (0x1UL << DCMI_CR_OUTEN_Pos)
5801 #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
5802 #define DCMI_CR_ENABLE_Pos (14U)
5803 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5804 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5805 #define DCMI_CR_BSM_0 0x00010000U
5806 #define DCMI_CR_BSM_1 0x00020000U
5807 #define DCMI_CR_OEBS_Pos (18U)
5808 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
5809 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5810 #define DCMI_CR_LSM_Pos (19U)
5811 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
5812 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
5813 #define DCMI_CR_OELS_Pos (20U)
5814 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
5815 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
5816 
5817 /******************** Bits definition for DCMI_SR register ******************/
5818 #define DCMI_SR_HSYNC_Pos (0U)
5819 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5820 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5821 #define DCMI_SR_VSYNC_Pos (1U)
5822 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5823 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5824 #define DCMI_SR_FNE_Pos (2U)
5825 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5826 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5827 
5828 /******************** Bits definition for DCMI_RIS register *****************/
5829 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5830 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5831 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5832 #define DCMI_RIS_OVR_RIS_Pos (1U)
5833 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5834 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5835 #define DCMI_RIS_ERR_RIS_Pos (2U)
5836 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5837 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5838 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5839 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5840 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5841 #define DCMI_RIS_LINE_RIS_Pos (4U)
5842 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5843 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5844 /* Legacy defines */
5845 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5846 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5847 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5848 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5849 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5850 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5851 
5852 /******************** Bits definition for DCMI_IER register *****************/
5853 #define DCMI_IER_FRAME_IE_Pos (0U)
5854 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5855 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5856 #define DCMI_IER_OVR_IE_Pos (1U)
5857 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5858 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5859 #define DCMI_IER_ERR_IE_Pos (2U)
5860 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5861 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5862 #define DCMI_IER_VSYNC_IE_Pos (3U)
5863 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5864 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5865 #define DCMI_IER_LINE_IE_Pos (4U)
5866 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5867 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5868 /* Legacy defines */
5869 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5870 
5871 /******************** Bits definition for DCMI_MIS register *****************/
5872 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5873 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5874 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5875 #define DCMI_MIS_OVR_MIS_Pos (1U)
5876 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5877 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5878 #define DCMI_MIS_ERR_MIS_Pos (2U)
5879 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5880 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5881 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5882 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5883 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5884 #define DCMI_MIS_LINE_MIS_Pos (4U)
5885 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5886 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5887 
5888 /* Legacy defines */
5889 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5890 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5891 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5892 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5893 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5894 
5895 /******************** Bits definition for DCMI_ICR register *****************/
5896 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5897 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5898 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5899 #define DCMI_ICR_OVR_ISC_Pos (1U)
5900 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5901 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5902 #define DCMI_ICR_ERR_ISC_Pos (2U)
5903 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5904 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5905 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5906 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5907 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5908 #define DCMI_ICR_LINE_ISC_Pos (4U)
5909 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5910 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5911 
5912 /* Legacy defines */
5913 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5914 
5915 /******************** Bits definition for DCMI_ESCR register ******************/
5916 #define DCMI_ESCR_FSC_Pos (0U)
5917 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5918 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5919 #define DCMI_ESCR_LSC_Pos (8U)
5920 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
5921 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5922 #define DCMI_ESCR_LEC_Pos (16U)
5923 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
5924 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5925 #define DCMI_ESCR_FEC_Pos (24U)
5926 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
5927 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5928 
5929 /******************** Bits definition for DCMI_ESUR register ******************/
5930 #define DCMI_ESUR_FSU_Pos (0U)
5931 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
5932 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5933 #define DCMI_ESUR_LSU_Pos (8U)
5934 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
5935 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5936 #define DCMI_ESUR_LEU_Pos (16U)
5937 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
5938 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5939 #define DCMI_ESUR_FEU_Pos (24U)
5940 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
5941 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5942 
5943 /******************** Bits definition for DCMI_CWSTRT register ******************/
5944 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5945 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
5946 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5947 #define DCMI_CWSTRT_VST_Pos (16U)
5948 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
5949 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5950 
5951 /******************** Bits definition for DCMI_CWSIZE register ******************/
5952 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
5953 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
5954 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5955 #define DCMI_CWSIZE_VLINE_Pos (16U)
5956 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
5957 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5958 
5959 /******************** Bits definition for DCMI_DR register *********************/
5960 #define DCMI_DR_BYTE0_Pos (0U)
5961 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
5962 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5963 #define DCMI_DR_BYTE1_Pos (8U)
5964 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
5965 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5966 #define DCMI_DR_BYTE2_Pos (16U)
5967 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
5968 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5969 #define DCMI_DR_BYTE3_Pos (24U)
5970 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
5971 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5972 
5973 /******************************************************************************/
5974 /* */
5975 /* DMA Controller */
5976 /* */
5977 /******************************************************************************/
5978 /******************** Bits definition for DMA_SxCR register *****************/
5979 #define DMA_SxCR_CHSEL_Pos (25U)
5980 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5981 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5982 #define DMA_SxCR_CHSEL_0 0x02000000U
5983 #define DMA_SxCR_CHSEL_1 0x04000000U
5984 #define DMA_SxCR_CHSEL_2 0x08000000U
5985 #define DMA_SxCR_MBURST_Pos (23U)
5986 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5987 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5988 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5989 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5990 #define DMA_SxCR_PBURST_Pos (21U)
5991 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5992 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5993 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5994 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5995 #define DMA_SxCR_CT_Pos (19U)
5996 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5997 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
5998 #define DMA_SxCR_DBM_Pos (18U)
5999 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6000 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6001 #define DMA_SxCR_PL_Pos (16U)
6002 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6003 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
6004 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6005 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6006 #define DMA_SxCR_PINCOS_Pos (15U)
6007 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6008 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6009 #define DMA_SxCR_MSIZE_Pos (13U)
6010 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6011 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6012 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6013 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6014 #define DMA_SxCR_PSIZE_Pos (11U)
6015 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6016 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6017 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6018 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6019 #define DMA_SxCR_MINC_Pos (10U)
6020 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6021 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6022 #define DMA_SxCR_PINC_Pos (9U)
6023 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6024 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6025 #define DMA_SxCR_CIRC_Pos (8U)
6026 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6027 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6028 #define DMA_SxCR_DIR_Pos (6U)
6029 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6030 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6031 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6032 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6033 #define DMA_SxCR_PFCTRL_Pos (5U)
6034 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6035 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6036 #define DMA_SxCR_TCIE_Pos (4U)
6037 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6038 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6039 #define DMA_SxCR_HTIE_Pos (3U)
6040 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6041 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6042 #define DMA_SxCR_TEIE_Pos (2U)
6043 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6044 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6045 #define DMA_SxCR_DMEIE_Pos (1U)
6046 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6047 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6048 #define DMA_SxCR_EN_Pos (0U)
6049 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6050 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6051 
6052 /* Legacy defines */
6053 #define DMA_SxCR_ACK_Pos (20U)
6054 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6055 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6056 
6057 /******************** Bits definition for DMA_SxCNDTR register **************/
6058 #define DMA_SxNDT_Pos (0U)
6059 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6060 #define DMA_SxNDT DMA_SxNDT_Msk
6061 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6062 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6063 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6064 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6065 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6066 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6067 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6068 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6069 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6070 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6071 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6072 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6073 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6074 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6075 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6076 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6078 /******************** Bits definition for DMA_SxFCR register ****************/
6079 #define DMA_SxFCR_FEIE_Pos (7U)
6080 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6081 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6082 #define DMA_SxFCR_FS_Pos (3U)
6083 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6084 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6085 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6086 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6087 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6088 #define DMA_SxFCR_DMDIS_Pos (2U)
6089 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6090 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6091 #define DMA_SxFCR_FTH_Pos (0U)
6092 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6093 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6094 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6095 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6097 /******************** Bits definition for DMA_LISR register *****************/
6098 #define DMA_LISR_TCIF3_Pos (27U)
6099 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6100 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6101 #define DMA_LISR_HTIF3_Pos (26U)
6102 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6103 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6104 #define DMA_LISR_TEIF3_Pos (25U)
6105 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6106 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6107 #define DMA_LISR_DMEIF3_Pos (24U)
6108 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6109 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6110 #define DMA_LISR_FEIF3_Pos (22U)
6111 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6112 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6113 #define DMA_LISR_TCIF2_Pos (21U)
6114 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6115 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6116 #define DMA_LISR_HTIF2_Pos (20U)
6117 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6118 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6119 #define DMA_LISR_TEIF2_Pos (19U)
6120 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6121 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6122 #define DMA_LISR_DMEIF2_Pos (18U)
6123 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6124 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6125 #define DMA_LISR_FEIF2_Pos (16U)
6126 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6127 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6128 #define DMA_LISR_TCIF1_Pos (11U)
6129 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6130 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6131 #define DMA_LISR_HTIF1_Pos (10U)
6132 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6133 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6134 #define DMA_LISR_TEIF1_Pos (9U)
6135 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6136 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6137 #define DMA_LISR_DMEIF1_Pos (8U)
6138 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6139 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6140 #define DMA_LISR_FEIF1_Pos (6U)
6141 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6142 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6143 #define DMA_LISR_TCIF0_Pos (5U)
6144 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6145 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6146 #define DMA_LISR_HTIF0_Pos (4U)
6147 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6148 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6149 #define DMA_LISR_TEIF0_Pos (3U)
6150 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6151 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6152 #define DMA_LISR_DMEIF0_Pos (2U)
6153 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6154 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6155 #define DMA_LISR_FEIF0_Pos (0U)
6156 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6157 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6158 
6159 /******************** Bits definition for DMA_HISR register *****************/
6160 #define DMA_HISR_TCIF7_Pos (27U)
6161 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6162 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6163 #define DMA_HISR_HTIF7_Pos (26U)
6164 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6165 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6166 #define DMA_HISR_TEIF7_Pos (25U)
6167 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6168 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6169 #define DMA_HISR_DMEIF7_Pos (24U)
6170 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6171 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6172 #define DMA_HISR_FEIF7_Pos (22U)
6173 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6174 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6175 #define DMA_HISR_TCIF6_Pos (21U)
6176 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6177 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6178 #define DMA_HISR_HTIF6_Pos (20U)
6179 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6180 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6181 #define DMA_HISR_TEIF6_Pos (19U)
6182 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6183 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6184 #define DMA_HISR_DMEIF6_Pos (18U)
6185 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6186 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6187 #define DMA_HISR_FEIF6_Pos (16U)
6188 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6189 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6190 #define DMA_HISR_TCIF5_Pos (11U)
6191 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6192 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6193 #define DMA_HISR_HTIF5_Pos (10U)
6194 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6195 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6196 #define DMA_HISR_TEIF5_Pos (9U)
6197 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6198 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6199 #define DMA_HISR_DMEIF5_Pos (8U)
6200 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6201 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6202 #define DMA_HISR_FEIF5_Pos (6U)
6203 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6204 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6205 #define DMA_HISR_TCIF4_Pos (5U)
6206 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6207 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6208 #define DMA_HISR_HTIF4_Pos (4U)
6209 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6210 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6211 #define DMA_HISR_TEIF4_Pos (3U)
6212 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6213 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6214 #define DMA_HISR_DMEIF4_Pos (2U)
6215 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6216 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6217 #define DMA_HISR_FEIF4_Pos (0U)
6218 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6219 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6220 
6221 /******************** Bits definition for DMA_LIFCR register ****************/
6222 #define DMA_LIFCR_CTCIF3_Pos (27U)
6223 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6224 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6225 #define DMA_LIFCR_CHTIF3_Pos (26U)
6226 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6227 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6228 #define DMA_LIFCR_CTEIF3_Pos (25U)
6229 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6230 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6231 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6232 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6233 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6234 #define DMA_LIFCR_CFEIF3_Pos (22U)
6235 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6236 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6237 #define DMA_LIFCR_CTCIF2_Pos (21U)
6238 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6239 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6240 #define DMA_LIFCR_CHTIF2_Pos (20U)
6241 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6242 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6243 #define DMA_LIFCR_CTEIF2_Pos (19U)
6244 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6245 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6246 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6247 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6248 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6249 #define DMA_LIFCR_CFEIF2_Pos (16U)
6250 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6251 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6252 #define DMA_LIFCR_CTCIF1_Pos (11U)
6253 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6254 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6255 #define DMA_LIFCR_CHTIF1_Pos (10U)
6256 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6257 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6258 #define DMA_LIFCR_CTEIF1_Pos (9U)
6259 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6260 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6261 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6262 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6263 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6264 #define DMA_LIFCR_CFEIF1_Pos (6U)
6265 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6266 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6267 #define DMA_LIFCR_CTCIF0_Pos (5U)
6268 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6269 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6270 #define DMA_LIFCR_CHTIF0_Pos (4U)
6271 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6272 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6273 #define DMA_LIFCR_CTEIF0_Pos (3U)
6274 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6275 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6276 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6277 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6278 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6279 #define DMA_LIFCR_CFEIF0_Pos (0U)
6280 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6281 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6282 
6283 /******************** Bits definition for DMA_HIFCR register ****************/
6284 #define DMA_HIFCR_CTCIF7_Pos (27U)
6285 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6286 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6287 #define DMA_HIFCR_CHTIF7_Pos (26U)
6288 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6289 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6290 #define DMA_HIFCR_CTEIF7_Pos (25U)
6291 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6292 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6293 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6294 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6295 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6296 #define DMA_HIFCR_CFEIF7_Pos (22U)
6297 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6298 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6299 #define DMA_HIFCR_CTCIF6_Pos (21U)
6300 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6301 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6302 #define DMA_HIFCR_CHTIF6_Pos (20U)
6303 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6304 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6305 #define DMA_HIFCR_CTEIF6_Pos (19U)
6306 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6307 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6308 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6309 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6310 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6311 #define DMA_HIFCR_CFEIF6_Pos (16U)
6312 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6313 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6314 #define DMA_HIFCR_CTCIF5_Pos (11U)
6315 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6316 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6317 #define DMA_HIFCR_CHTIF5_Pos (10U)
6318 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6319 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6320 #define DMA_HIFCR_CTEIF5_Pos (9U)
6321 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6322 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6323 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6324 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6325 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6326 #define DMA_HIFCR_CFEIF5_Pos (6U)
6327 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6328 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6329 #define DMA_HIFCR_CTCIF4_Pos (5U)
6330 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6331 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6332 #define DMA_HIFCR_CHTIF4_Pos (4U)
6333 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6334 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6335 #define DMA_HIFCR_CTEIF4_Pos (3U)
6336 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6337 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6338 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6339 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6340 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6341 #define DMA_HIFCR_CFEIF4_Pos (0U)
6342 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6343 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6344 
6345 /****************** Bit definition for DMA_SxPAR register ********************/
6346 #define DMA_SxPAR_PA_Pos (0U)
6347 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6348 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6350 /****************** Bit definition for DMA_SxM0AR register ********************/
6351 #define DMA_SxM0AR_M0A_Pos (0U)
6352 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6353 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6355 /****************** Bit definition for DMA_SxM1AR register ********************/
6356 #define DMA_SxM1AR_M1A_Pos (0U)
6357 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6358 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6361 /******************************************************************************/
6362 /* */
6363 /* External Interrupt/Event Controller */
6364 /* */
6365 /******************************************************************************/
6366 /******************* Bit definition for EXTI_IMR register *******************/
6367 #define EXTI_IMR_MR0_Pos (0U)
6368 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6369 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6370 #define EXTI_IMR_MR1_Pos (1U)
6371 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6372 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6373 #define EXTI_IMR_MR2_Pos (2U)
6374 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6375 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6376 #define EXTI_IMR_MR3_Pos (3U)
6377 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6378 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6379 #define EXTI_IMR_MR4_Pos (4U)
6380 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6381 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6382 #define EXTI_IMR_MR5_Pos (5U)
6383 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6384 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6385 #define EXTI_IMR_MR6_Pos (6U)
6386 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6387 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6388 #define EXTI_IMR_MR7_Pos (7U)
6389 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6390 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6391 #define EXTI_IMR_MR8_Pos (8U)
6392 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6393 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6394 #define EXTI_IMR_MR9_Pos (9U)
6395 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6396 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6397 #define EXTI_IMR_MR10_Pos (10U)
6398 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6399 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6400 #define EXTI_IMR_MR11_Pos (11U)
6401 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6402 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6403 #define EXTI_IMR_MR12_Pos (12U)
6404 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6405 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6406 #define EXTI_IMR_MR13_Pos (13U)
6407 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6408 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6409 #define EXTI_IMR_MR14_Pos (14U)
6410 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6411 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6412 #define EXTI_IMR_MR15_Pos (15U)
6413 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6414 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6415 #define EXTI_IMR_MR16_Pos (16U)
6416 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6417 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6418 #define EXTI_IMR_MR17_Pos (17U)
6419 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6420 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6421 #define EXTI_IMR_MR18_Pos (18U)
6422 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6423 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6424 #define EXTI_IMR_MR19_Pos (19U)
6425 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6426 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6427 #define EXTI_IMR_MR20_Pos (20U)
6428 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6429 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6430 #define EXTI_IMR_MR21_Pos (21U)
6431 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6432 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6433 #define EXTI_IMR_MR22_Pos (22U)
6434 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6435 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6437 /* Reference Defines */
6438 #define EXTI_IMR_IM0 EXTI_IMR_MR0
6439 #define EXTI_IMR_IM1 EXTI_IMR_MR1
6440 #define EXTI_IMR_IM2 EXTI_IMR_MR2
6441 #define EXTI_IMR_IM3 EXTI_IMR_MR3
6442 #define EXTI_IMR_IM4 EXTI_IMR_MR4
6443 #define EXTI_IMR_IM5 EXTI_IMR_MR5
6444 #define EXTI_IMR_IM6 EXTI_IMR_MR6
6445 #define EXTI_IMR_IM7 EXTI_IMR_MR7
6446 #define EXTI_IMR_IM8 EXTI_IMR_MR8
6447 #define EXTI_IMR_IM9 EXTI_IMR_MR9
6448 #define EXTI_IMR_IM10 EXTI_IMR_MR10
6449 #define EXTI_IMR_IM11 EXTI_IMR_MR11
6450 #define EXTI_IMR_IM12 EXTI_IMR_MR12
6451 #define EXTI_IMR_IM13 EXTI_IMR_MR13
6452 #define EXTI_IMR_IM14 EXTI_IMR_MR14
6453 #define EXTI_IMR_IM15 EXTI_IMR_MR15
6454 #define EXTI_IMR_IM16 EXTI_IMR_MR16
6455 #define EXTI_IMR_IM17 EXTI_IMR_MR17
6456 #define EXTI_IMR_IM18 EXTI_IMR_MR18
6457 #define EXTI_IMR_IM19 EXTI_IMR_MR19
6458 #define EXTI_IMR_IM20 EXTI_IMR_MR20
6459 #define EXTI_IMR_IM21 EXTI_IMR_MR21
6460 #define EXTI_IMR_IM22 EXTI_IMR_MR22
6461 #define EXTI_IMR_IM_Pos (0U)
6462 #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6463 #define EXTI_IMR_IM EXTI_IMR_IM_Msk
6465 /******************* Bit definition for EXTI_EMR register *******************/
6466 #define EXTI_EMR_MR0_Pos (0U)
6467 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6468 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6469 #define EXTI_EMR_MR1_Pos (1U)
6470 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6471 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6472 #define EXTI_EMR_MR2_Pos (2U)
6473 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6474 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6475 #define EXTI_EMR_MR3_Pos (3U)
6476 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6477 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6478 #define EXTI_EMR_MR4_Pos (4U)
6479 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6480 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6481 #define EXTI_EMR_MR5_Pos (5U)
6482 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6483 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6484 #define EXTI_EMR_MR6_Pos (6U)
6485 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6486 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6487 #define EXTI_EMR_MR7_Pos (7U)
6488 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6489 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6490 #define EXTI_EMR_MR8_Pos (8U)
6491 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6492 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6493 #define EXTI_EMR_MR9_Pos (9U)
6494 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6495 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6496 #define EXTI_EMR_MR10_Pos (10U)
6497 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6498 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6499 #define EXTI_EMR_MR11_Pos (11U)
6500 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6501 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6502 #define EXTI_EMR_MR12_Pos (12U)
6503 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6504 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6505 #define EXTI_EMR_MR13_Pos (13U)
6506 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6507 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6508 #define EXTI_EMR_MR14_Pos (14U)
6509 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6510 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6511 #define EXTI_EMR_MR15_Pos (15U)
6512 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6513 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6514 #define EXTI_EMR_MR16_Pos (16U)
6515 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6516 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6517 #define EXTI_EMR_MR17_Pos (17U)
6518 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6519 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6520 #define EXTI_EMR_MR18_Pos (18U)
6521 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6522 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6523 #define EXTI_EMR_MR19_Pos (19U)
6524 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6525 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6526 #define EXTI_EMR_MR20_Pos (20U)
6527 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6528 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6529 #define EXTI_EMR_MR21_Pos (21U)
6530 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6531 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6532 #define EXTI_EMR_MR22_Pos (22U)
6533 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6534 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6536 /* Reference Defines */
6537 #define EXTI_EMR_EM0 EXTI_EMR_MR0
6538 #define EXTI_EMR_EM1 EXTI_EMR_MR1
6539 #define EXTI_EMR_EM2 EXTI_EMR_MR2
6540 #define EXTI_EMR_EM3 EXTI_EMR_MR3
6541 #define EXTI_EMR_EM4 EXTI_EMR_MR4
6542 #define EXTI_EMR_EM5 EXTI_EMR_MR5
6543 #define EXTI_EMR_EM6 EXTI_EMR_MR6
6544 #define EXTI_EMR_EM7 EXTI_EMR_MR7
6545 #define EXTI_EMR_EM8 EXTI_EMR_MR8
6546 #define EXTI_EMR_EM9 EXTI_EMR_MR9
6547 #define EXTI_EMR_EM10 EXTI_EMR_MR10
6548 #define EXTI_EMR_EM11 EXTI_EMR_MR11
6549 #define EXTI_EMR_EM12 EXTI_EMR_MR12
6550 #define EXTI_EMR_EM13 EXTI_EMR_MR13
6551 #define EXTI_EMR_EM14 EXTI_EMR_MR14
6552 #define EXTI_EMR_EM15 EXTI_EMR_MR15
6553 #define EXTI_EMR_EM16 EXTI_EMR_MR16
6554 #define EXTI_EMR_EM17 EXTI_EMR_MR17
6555 #define EXTI_EMR_EM18 EXTI_EMR_MR18
6556 #define EXTI_EMR_EM19 EXTI_EMR_MR19
6557 #define EXTI_EMR_EM20 EXTI_EMR_MR20
6558 #define EXTI_EMR_EM21 EXTI_EMR_MR21
6559 #define EXTI_EMR_EM22 EXTI_EMR_MR22
6560 
6561 /****************** Bit definition for EXTI_RTSR register *******************/
6562 #define EXTI_RTSR_TR0_Pos (0U)
6563 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6564 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6565 #define EXTI_RTSR_TR1_Pos (1U)
6566 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6567 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6568 #define EXTI_RTSR_TR2_Pos (2U)
6569 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6570 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6571 #define EXTI_RTSR_TR3_Pos (3U)
6572 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6573 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6574 #define EXTI_RTSR_TR4_Pos (4U)
6575 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6576 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6577 #define EXTI_RTSR_TR5_Pos (5U)
6578 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6579 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6580 #define EXTI_RTSR_TR6_Pos (6U)
6581 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6582 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6583 #define EXTI_RTSR_TR7_Pos (7U)
6584 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6585 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6586 #define EXTI_RTSR_TR8_Pos (8U)
6587 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6588 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6589 #define EXTI_RTSR_TR9_Pos (9U)
6590 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6591 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6592 #define EXTI_RTSR_TR10_Pos (10U)
6593 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6594 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6595 #define EXTI_RTSR_TR11_Pos (11U)
6596 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6597 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6598 #define EXTI_RTSR_TR12_Pos (12U)
6599 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6600 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6601 #define EXTI_RTSR_TR13_Pos (13U)
6602 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6603 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6604 #define EXTI_RTSR_TR14_Pos (14U)
6605 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6606 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6607 #define EXTI_RTSR_TR15_Pos (15U)
6608 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6609 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6610 #define EXTI_RTSR_TR16_Pos (16U)
6611 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6612 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6613 #define EXTI_RTSR_TR17_Pos (17U)
6614 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6615 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6616 #define EXTI_RTSR_TR18_Pos (18U)
6617 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6618 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6619 #define EXTI_RTSR_TR19_Pos (19U)
6620 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6621 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6622 #define EXTI_RTSR_TR20_Pos (20U)
6623 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6624 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6625 #define EXTI_RTSR_TR21_Pos (21U)
6626 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6627 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6628 #define EXTI_RTSR_TR22_Pos (22U)
6629 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6630 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6632 /****************** Bit definition for EXTI_FTSR register *******************/
6633 #define EXTI_FTSR_TR0_Pos (0U)
6634 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6635 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6636 #define EXTI_FTSR_TR1_Pos (1U)
6637 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6638 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6639 #define EXTI_FTSR_TR2_Pos (2U)
6640 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6641 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6642 #define EXTI_FTSR_TR3_Pos (3U)
6643 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6644 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6645 #define EXTI_FTSR_TR4_Pos (4U)
6646 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6647 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6648 #define EXTI_FTSR_TR5_Pos (5U)
6649 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6650 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6651 #define EXTI_FTSR_TR6_Pos (6U)
6652 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6653 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6654 #define EXTI_FTSR_TR7_Pos (7U)
6655 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6656 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6657 #define EXTI_FTSR_TR8_Pos (8U)
6658 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6659 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6660 #define EXTI_FTSR_TR9_Pos (9U)
6661 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6662 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6663 #define EXTI_FTSR_TR10_Pos (10U)
6664 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6665 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6666 #define EXTI_FTSR_TR11_Pos (11U)
6667 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6668 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6669 #define EXTI_FTSR_TR12_Pos (12U)
6670 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6671 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6672 #define EXTI_FTSR_TR13_Pos (13U)
6673 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6674 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6675 #define EXTI_FTSR_TR14_Pos (14U)
6676 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6677 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6678 #define EXTI_FTSR_TR15_Pos (15U)
6679 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6680 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6681 #define EXTI_FTSR_TR16_Pos (16U)
6682 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6683 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6684 #define EXTI_FTSR_TR17_Pos (17U)
6685 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6686 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6687 #define EXTI_FTSR_TR18_Pos (18U)
6688 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6689 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6690 #define EXTI_FTSR_TR19_Pos (19U)
6691 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6692 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6693 #define EXTI_FTSR_TR20_Pos (20U)
6694 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6695 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6696 #define EXTI_FTSR_TR21_Pos (21U)
6697 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6698 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6699 #define EXTI_FTSR_TR22_Pos (22U)
6700 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6701 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6703 /****************** Bit definition for EXTI_SWIER register ******************/
6704 #define EXTI_SWIER_SWIER0_Pos (0U)
6705 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6706 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6707 #define EXTI_SWIER_SWIER1_Pos (1U)
6708 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6709 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6710 #define EXTI_SWIER_SWIER2_Pos (2U)
6711 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6712 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6713 #define EXTI_SWIER_SWIER3_Pos (3U)
6714 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6715 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6716 #define EXTI_SWIER_SWIER4_Pos (4U)
6717 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6718 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6719 #define EXTI_SWIER_SWIER5_Pos (5U)
6720 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6721 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6722 #define EXTI_SWIER_SWIER6_Pos (6U)
6723 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6724 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6725 #define EXTI_SWIER_SWIER7_Pos (7U)
6726 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6727 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6728 #define EXTI_SWIER_SWIER8_Pos (8U)
6729 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6730 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6731 #define EXTI_SWIER_SWIER9_Pos (9U)
6732 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6733 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6734 #define EXTI_SWIER_SWIER10_Pos (10U)
6735 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6736 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6737 #define EXTI_SWIER_SWIER11_Pos (11U)
6738 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6739 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6740 #define EXTI_SWIER_SWIER12_Pos (12U)
6741 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6742 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6743 #define EXTI_SWIER_SWIER13_Pos (13U)
6744 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6745 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6746 #define EXTI_SWIER_SWIER14_Pos (14U)
6747 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6748 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6749 #define EXTI_SWIER_SWIER15_Pos (15U)
6750 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6751 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6752 #define EXTI_SWIER_SWIER16_Pos (16U)
6753 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6754 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6755 #define EXTI_SWIER_SWIER17_Pos (17U)
6756 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6757 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6758 #define EXTI_SWIER_SWIER18_Pos (18U)
6759 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6760 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6761 #define EXTI_SWIER_SWIER19_Pos (19U)
6762 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6763 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6764 #define EXTI_SWIER_SWIER20_Pos (20U)
6765 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6766 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6767 #define EXTI_SWIER_SWIER21_Pos (21U)
6768 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6769 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6770 #define EXTI_SWIER_SWIER22_Pos (22U)
6771 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6772 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6774 /******************* Bit definition for EXTI_PR register ********************/
6775 #define EXTI_PR_PR0_Pos (0U)
6776 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6777 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6778 #define EXTI_PR_PR1_Pos (1U)
6779 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6780 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6781 #define EXTI_PR_PR2_Pos (2U)
6782 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6783 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6784 #define EXTI_PR_PR3_Pos (3U)
6785 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6786 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6787 #define EXTI_PR_PR4_Pos (4U)
6788 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6789 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6790 #define EXTI_PR_PR5_Pos (5U)
6791 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6792 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6793 #define EXTI_PR_PR6_Pos (6U)
6794 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6795 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6796 #define EXTI_PR_PR7_Pos (7U)
6797 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6798 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6799 #define EXTI_PR_PR8_Pos (8U)
6800 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6801 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6802 #define EXTI_PR_PR9_Pos (9U)
6803 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6804 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6805 #define EXTI_PR_PR10_Pos (10U)
6806 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6807 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6808 #define EXTI_PR_PR11_Pos (11U)
6809 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6810 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6811 #define EXTI_PR_PR12_Pos (12U)
6812 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6813 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6814 #define EXTI_PR_PR13_Pos (13U)
6815 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6816 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6817 #define EXTI_PR_PR14_Pos (14U)
6818 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6819 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6820 #define EXTI_PR_PR15_Pos (15U)
6821 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6822 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6823 #define EXTI_PR_PR16_Pos (16U)
6824 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6825 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6826 #define EXTI_PR_PR17_Pos (17U)
6827 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6828 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6829 #define EXTI_PR_PR18_Pos (18U)
6830 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6831 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6832 #define EXTI_PR_PR19_Pos (19U)
6833 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6834 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6835 #define EXTI_PR_PR20_Pos (20U)
6836 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6837 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6838 #define EXTI_PR_PR21_Pos (21U)
6839 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6840 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6841 #define EXTI_PR_PR22_Pos (22U)
6842 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6843 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6845 /******************************************************************************/
6846 /* */
6847 /* FLASH */
6848 /* */
6849 /******************************************************************************/
6850 /******************* Bits definition for FLASH_ACR register *****************/
6851 #define FLASH_ACR_LATENCY_Pos (0U)
6852 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
6853 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6854 #define FLASH_ACR_LATENCY_0WS 0x00000000U
6855 #define FLASH_ACR_LATENCY_1WS 0x00000001U
6856 #define FLASH_ACR_LATENCY_2WS 0x00000002U
6857 #define FLASH_ACR_LATENCY_3WS 0x00000003U
6858 #define FLASH_ACR_LATENCY_4WS 0x00000004U
6859 #define FLASH_ACR_LATENCY_5WS 0x00000005U
6860 #define FLASH_ACR_LATENCY_6WS 0x00000006U
6861 #define FLASH_ACR_LATENCY_7WS 0x00000007U
6862 
6863 #define FLASH_ACR_LATENCY_8WS 0x00000008U
6864 #define FLASH_ACR_LATENCY_9WS 0x00000009U
6865 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
6866 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
6867 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
6868 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
6869 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
6870 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
6871 
6872 #define FLASH_ACR_PRFTEN_Pos (8U)
6873 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6874 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6875 #define FLASH_ACR_ICEN_Pos (9U)
6876 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6877 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6878 #define FLASH_ACR_DCEN_Pos (10U)
6879 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6880 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6881 #define FLASH_ACR_ICRST_Pos (11U)
6882 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6883 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6884 #define FLASH_ACR_DCRST_Pos (12U)
6885 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6886 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6887 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6888 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6889 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6890 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6891 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6892 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6893 
6894 /******************* Bits definition for FLASH_SR register ******************/
6895 #define FLASH_SR_EOP_Pos (0U)
6896 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6897 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
6898 #define FLASH_SR_SOP_Pos (1U)
6899 #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
6900 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
6901 #define FLASH_SR_WRPERR_Pos (4U)
6902 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6903 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6904 #define FLASH_SR_PGAERR_Pos (5U)
6905 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6906 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6907 #define FLASH_SR_PGPERR_Pos (6U)
6908 #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6909 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6910 #define FLASH_SR_PGSERR_Pos (7U)
6911 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6912 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6913 #define FLASH_SR_RDERR_Pos (8U)
6914 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
6915 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6916 #define FLASH_SR_BSY_Pos (16U)
6917 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6918 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
6919 
6920 /******************* Bits definition for FLASH_CR register ******************/
6921 #define FLASH_CR_PG_Pos (0U)
6922 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6923 #define FLASH_CR_PG FLASH_CR_PG_Msk
6924 #define FLASH_CR_SER_Pos (1U)
6925 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6926 #define FLASH_CR_SER FLASH_CR_SER_Msk
6927 #define FLASH_CR_MER_Pos (2U)
6928 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6929 #define FLASH_CR_MER FLASH_CR_MER_Msk
6930 #define FLASH_CR_MER1 FLASH_CR_MER
6931 #define FLASH_CR_SNB_Pos (3U)
6932 #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
6933 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
6934 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6935 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6936 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6937 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6938 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
6939 #define FLASH_CR_PSIZE_Pos (8U)
6940 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6941 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6942 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6943 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6944 #define FLASH_CR_MER2_Pos (15U)
6945 #define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
6946 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
6947 #define FLASH_CR_STRT_Pos (16U)
6948 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6949 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
6950 #define FLASH_CR_EOPIE_Pos (24U)
6951 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6952 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6953 #define FLASH_CR_ERRIE_Pos (25U)
6954 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6955 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6956 #define FLASH_CR_LOCK_Pos (31U)
6957 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6958 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6959 
6960 /******************* Bits definition for FLASH_OPTCR register ***************/
6961 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
6962 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6963 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6964 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
6965 #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6966 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6967 
6968 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6969 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6970 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
6971 #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6972 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6973 #define FLASH_OPTCR_BFB2_Pos (4U)
6974 #define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos)
6975 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
6976 #define FLASH_OPTCR_WDG_SW_Pos (5U)
6977 #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6978 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6979 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
6980 #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6981 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6982 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6983 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6984 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6985 #define FLASH_OPTCR_RDP_Pos (8U)
6986 #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6987 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6988 #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6989 #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6990 #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6991 #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6992 #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6993 #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6994 #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6995 #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6996 #define FLASH_OPTCR_nWRP_Pos (16U)
6997 #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
6998 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6999 #define FLASH_OPTCR_nWRP_0 0x00010000U
7000 #define FLASH_OPTCR_nWRP_1 0x00020000U
7001 #define FLASH_OPTCR_nWRP_2 0x00040000U
7002 #define FLASH_OPTCR_nWRP_3 0x00080000U
7003 #define FLASH_OPTCR_nWRP_4 0x00100000U
7004 #define FLASH_OPTCR_nWRP_5 0x00200000U
7005 #define FLASH_OPTCR_nWRP_6 0x00400000U
7006 #define FLASH_OPTCR_nWRP_7 0x00800000U
7007 #define FLASH_OPTCR_nWRP_8 0x01000000U
7008 #define FLASH_OPTCR_nWRP_9 0x02000000U
7009 #define FLASH_OPTCR_nWRP_10 0x04000000U
7010 #define FLASH_OPTCR_nWRP_11 0x08000000U
7011 #define FLASH_OPTCR_DB1M_Pos (30U)
7012 #define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos)
7013 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
7014 #define FLASH_OPTCR_SPRMOD_Pos (31U)
7015 #define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos)
7016 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
7017 
7018 /****************** Bits definition for FLASH_OPTCR1 register ***************/
7019 #define FLASH_OPTCR1_nWRP_Pos (16U)
7020 #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
7021 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7022 #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
7023 #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
7024 #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
7025 #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
7026 #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
7027 #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
7028 #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
7029 #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
7030 #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
7031 #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
7032 #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
7033 #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
7035 /******************************************************************************/
7036 /* */
7037 /* Flexible Memory Controller */
7038 /* */
7039 /******************************************************************************/
7040 /****************** Bit definition for FMC_BCR1 register *******************/
7041 #define FMC_BCR1_MBKEN_Pos (0U)
7042 #define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
7043 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
7044 #define FMC_BCR1_MUXEN_Pos (1U)
7045 #define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
7046 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
7048 #define FMC_BCR1_MTYP_Pos (2U)
7049 #define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
7050 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
7051 #define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
7052 #define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
7054 #define FMC_BCR1_MWID_Pos (4U)
7055 #define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
7056 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
7057 #define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
7058 #define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
7060 #define FMC_BCR1_FACCEN_Pos (6U)
7061 #define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
7062 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
7063 #define FMC_BCR1_BURSTEN_Pos (8U)
7064 #define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
7065 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
7066 #define FMC_BCR1_WAITPOL_Pos (9U)
7067 #define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
7068 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
7069 #define FMC_BCR1_WAITCFG_Pos (11U)
7070 #define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
7071 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
7072 #define FMC_BCR1_WREN_Pos (12U)
7073 #define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
7074 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
7075 #define FMC_BCR1_WAITEN_Pos (13U)
7076 #define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
7077 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
7078 #define FMC_BCR1_EXTMOD_Pos (14U)
7079 #define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
7080 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
7081 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
7082 #define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
7083 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
7084 #define FMC_BCR1_CPSIZE_Pos (16U)
7085 #define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
7086 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
7087 #define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
7088 #define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
7089 #define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
7090 #define FMC_BCR1_CBURSTRW_Pos (19U)
7091 #define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
7092 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
7093 #define FMC_BCR1_CCLKEN_Pos (20U)
7094 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7095 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7096 #define FMC_BCR1_WFDIS_Pos (21U)
7097 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
7098 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
7100 /****************** Bit definition for FMC_BCR2 register *******************/
7101 #define FMC_BCR2_MBKEN_Pos (0U)
7102 #define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
7103 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
7104 #define FMC_BCR2_MUXEN_Pos (1U)
7105 #define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
7106 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
7108 #define FMC_BCR2_MTYP_Pos (2U)
7109 #define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
7110 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
7111 #define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
7112 #define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
7114 #define FMC_BCR2_MWID_Pos (4U)
7115 #define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
7116 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
7117 #define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
7118 #define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
7120 #define FMC_BCR2_FACCEN_Pos (6U)
7121 #define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
7122 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
7123 #define FMC_BCR2_BURSTEN_Pos (8U)
7124 #define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
7125 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
7126 #define FMC_BCR2_WAITPOL_Pos (9U)
7127 #define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
7128 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
7129 #define FMC_BCR2_WAITCFG_Pos (11U)
7130 #define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
7131 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
7132 #define FMC_BCR2_WREN_Pos (12U)
7133 #define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
7134 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
7135 #define FMC_BCR2_WAITEN_Pos (13U)
7136 #define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
7137 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
7138 #define FMC_BCR2_EXTMOD_Pos (14U)
7139 #define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
7140 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
7141 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
7142 #define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
7143 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
7144 #define FMC_BCR2_CBURSTRW_Pos (19U)
7145 #define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
7146 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
7148 /****************** Bit definition for FMC_BCR3 register *******************/
7149 #define FMC_BCR3_MBKEN_Pos (0U)
7150 #define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
7151 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
7152 #define FMC_BCR3_MUXEN_Pos (1U)
7153 #define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
7154 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
7156 #define FMC_BCR3_MTYP_Pos (2U)
7157 #define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
7158 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
7159 #define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
7160 #define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
7162 #define FMC_BCR3_MWID_Pos (4U)
7163 #define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
7164 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
7165 #define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
7166 #define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
7168 #define FMC_BCR3_FACCEN_Pos (6U)
7169 #define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
7170 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
7171 #define FMC_BCR3_BURSTEN_Pos (8U)
7172 #define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
7173 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
7174 #define FMC_BCR3_WAITPOL_Pos (9U)
7175 #define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
7176 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
7177 #define FMC_BCR3_WAITCFG_Pos (11U)
7178 #define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
7179 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
7180 #define FMC_BCR3_WREN_Pos (12U)
7181 #define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
7182 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
7183 #define FMC_BCR3_WAITEN_Pos (13U)
7184 #define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
7185 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
7186 #define FMC_BCR3_EXTMOD_Pos (14U)
7187 #define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
7188 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
7189 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
7190 #define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
7191 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
7192 #define FMC_BCR3_CBURSTRW_Pos (19U)
7193 #define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
7194 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
7196 /****************** Bit definition for FMC_BCR4 register *******************/
7197 #define FMC_BCR4_MBKEN_Pos (0U)
7198 #define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
7199 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
7200 #define FMC_BCR4_MUXEN_Pos (1U)
7201 #define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
7202 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
7204 #define FMC_BCR4_MTYP_Pos (2U)
7205 #define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
7206 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
7207 #define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
7208 #define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
7210 #define FMC_BCR4_MWID_Pos (4U)
7211 #define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
7212 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
7213 #define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
7214 #define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
7216 #define FMC_BCR4_FACCEN_Pos (6U)
7217 #define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
7218 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
7219 #define FMC_BCR4_BURSTEN_Pos (8U)
7220 #define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
7221 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
7222 #define FMC_BCR4_WAITPOL_Pos (9U)
7223 #define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
7224 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
7225 #define FMC_BCR4_WAITCFG_Pos (11U)
7226 #define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
7227 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
7228 #define FMC_BCR4_WREN_Pos (12U)
7229 #define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
7230 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
7231 #define FMC_BCR4_WAITEN_Pos (13U)
7232 #define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
7233 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
7234 #define FMC_BCR4_EXTMOD_Pos (14U)
7235 #define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
7236 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
7237 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
7238 #define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
7239 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
7240 #define FMC_BCR4_CBURSTRW_Pos (19U)
7241 #define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
7242 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
7244 /****************** Bit definition for FMC_BTR1 register ******************/
7245 #define FMC_BTR1_ADDSET_Pos (0U)
7246 #define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
7247 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
7248 #define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
7249 #define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
7250 #define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
7251 #define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
7253 #define FMC_BTR1_ADDHLD_Pos (4U)
7254 #define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
7255 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
7256 #define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
7257 #define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
7258 #define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
7259 #define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
7261 #define FMC_BTR1_DATAST_Pos (8U)
7262 #define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
7263 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
7264 #define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
7265 #define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
7266 #define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
7267 #define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
7268 #define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
7269 #define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
7270 #define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
7271 #define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
7273 #define FMC_BTR1_BUSTURN_Pos (16U)
7274 #define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
7275 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
7276 #define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
7277 #define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
7278 #define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
7279 #define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
7281 #define FMC_BTR1_CLKDIV_Pos (20U)
7282 #define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
7283 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
7284 #define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
7285 #define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
7286 #define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
7287 #define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
7289 #define FMC_BTR1_DATLAT_Pos (24U)
7290 #define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
7291 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
7292 #define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
7293 #define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
7294 #define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
7295 #define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
7297 #define FMC_BTR1_ACCMOD_Pos (28U)
7298 #define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
7299 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
7300 #define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
7301 #define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
7303 /****************** Bit definition for FMC_BTR2 register *******************/
7304 #define FMC_BTR2_ADDSET_Pos (0U)
7305 #define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
7306 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
7307 #define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
7308 #define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
7309 #define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
7310 #define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
7312 #define FMC_BTR2_ADDHLD_Pos (4U)
7313 #define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
7314 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
7315 #define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
7316 #define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
7317 #define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
7318 #define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
7320 #define FMC_BTR2_DATAST_Pos (8U)
7321 #define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
7322 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
7323 #define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
7324 #define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
7325 #define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
7326 #define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
7327 #define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
7328 #define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
7329 #define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
7330 #define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
7332 #define FMC_BTR2_BUSTURN_Pos (16U)
7333 #define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
7334 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
7335 #define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
7336 #define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
7337 #define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
7338 #define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
7340 #define FMC_BTR2_CLKDIV_Pos (20U)
7341 #define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
7342 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
7343 #define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
7344 #define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
7345 #define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
7346 #define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
7348 #define FMC_BTR2_DATLAT_Pos (24U)
7349 #define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
7350 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
7351 #define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
7352 #define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
7353 #define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
7354 #define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
7356 #define FMC_BTR2_ACCMOD_Pos (28U)
7357 #define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
7358 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
7359 #define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
7360 #define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
7362 /******************* Bit definition for FMC_BTR3 register *******************/
7363 #define FMC_BTR3_ADDSET_Pos (0U)
7364 #define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
7365 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
7366 #define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
7367 #define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
7368 #define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
7369 #define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
7371 #define FMC_BTR3_ADDHLD_Pos (4U)
7372 #define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
7373 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
7374 #define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
7375 #define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
7376 #define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
7377 #define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
7379 #define FMC_BTR3_DATAST_Pos (8U)
7380 #define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
7381 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
7382 #define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
7383 #define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
7384 #define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
7385 #define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
7386 #define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
7387 #define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
7388 #define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
7389 #define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
7391 #define FMC_BTR3_BUSTURN_Pos (16U)
7392 #define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
7393 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
7394 #define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
7395 #define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
7396 #define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
7397 #define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
7399 #define FMC_BTR3_CLKDIV_Pos (20U)
7400 #define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
7401 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
7402 #define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
7403 #define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
7404 #define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
7405 #define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
7407 #define FMC_BTR3_DATLAT_Pos (24U)
7408 #define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
7409 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
7410 #define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
7411 #define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
7412 #define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
7413 #define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
7415 #define FMC_BTR3_ACCMOD_Pos (28U)
7416 #define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
7417 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
7418 #define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
7419 #define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
7421 /****************** Bit definition for FMC_BTR4 register *******************/
7422 #define FMC_BTR4_ADDSET_Pos (0U)
7423 #define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
7424 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
7425 #define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
7426 #define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
7427 #define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
7428 #define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
7430 #define FMC_BTR4_ADDHLD_Pos (4U)
7431 #define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
7432 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
7433 #define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
7434 #define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
7435 #define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
7436 #define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
7438 #define FMC_BTR4_DATAST_Pos (8U)
7439 #define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
7440 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
7441 #define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
7442 #define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
7443 #define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
7444 #define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
7445 #define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
7446 #define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
7447 #define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
7448 #define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
7450 #define FMC_BTR4_BUSTURN_Pos (16U)
7451 #define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
7452 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
7453 #define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
7454 #define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
7455 #define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
7456 #define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
7458 #define FMC_BTR4_CLKDIV_Pos (20U)
7459 #define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
7460 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
7461 #define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
7462 #define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
7463 #define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
7464 #define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
7466 #define FMC_BTR4_DATLAT_Pos (24U)
7467 #define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
7468 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
7469 #define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
7470 #define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
7471 #define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
7472 #define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
7474 #define FMC_BTR4_ACCMOD_Pos (28U)
7475 #define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
7476 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
7477 #define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
7478 #define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
7480 /****************** Bit definition for FMC_BWTR1 register ******************/
7481 #define FMC_BWTR1_ADDSET_Pos (0U)
7482 #define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
7483 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
7484 #define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
7485 #define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
7486 #define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
7487 #define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
7489 #define FMC_BWTR1_ADDHLD_Pos (4U)
7490 #define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
7491 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
7492 #define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
7493 #define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
7494 #define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
7495 #define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
7497 #define FMC_BWTR1_DATAST_Pos (8U)
7498 #define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
7499 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
7500 #define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
7501 #define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
7502 #define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
7503 #define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
7504 #define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
7505 #define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
7506 #define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
7507 #define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
7509 #define FMC_BWTR1_BUSTURN_Pos (16U)
7510 #define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
7511 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
7512 #define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
7513 #define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
7514 #define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
7515 #define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
7517 #define FMC_BWTR1_ACCMOD_Pos (28U)
7518 #define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
7519 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
7520 #define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
7521 #define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
7523 /****************** Bit definition for FMC_BWTR2 register ******************/
7524 #define FMC_BWTR2_ADDSET_Pos (0U)
7525 #define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
7526 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
7527 #define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
7528 #define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
7529 #define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
7530 #define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
7532 #define FMC_BWTR2_ADDHLD_Pos (4U)
7533 #define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
7534 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
7535 #define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
7536 #define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
7537 #define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
7538 #define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
7540 #define FMC_BWTR2_DATAST_Pos (8U)
7541 #define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
7542 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
7543 #define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
7544 #define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
7545 #define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
7546 #define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
7547 #define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
7548 #define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
7549 #define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
7550 #define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
7552 #define FMC_BWTR2_BUSTURN_Pos (16U)
7553 #define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
7554 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
7555 #define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
7556 #define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
7557 #define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
7558 #define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
7560 #define FMC_BWTR2_ACCMOD_Pos (28U)
7561 #define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
7562 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
7563 #define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
7564 #define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
7566 /****************** Bit definition for FMC_BWTR3 register ******************/
7567 #define FMC_BWTR3_ADDSET_Pos (0U)
7568 #define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
7569 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
7570 #define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
7571 #define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
7572 #define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
7573 #define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
7575 #define FMC_BWTR3_ADDHLD_Pos (4U)
7576 #define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
7577 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
7578 #define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
7579 #define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
7580 #define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
7581 #define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
7583 #define FMC_BWTR3_DATAST_Pos (8U)
7584 #define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
7585 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
7586 #define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
7587 #define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
7588 #define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
7589 #define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
7590 #define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
7591 #define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
7592 #define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
7593 #define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
7595 #define FMC_BWTR3_BUSTURN_Pos (16U)
7596 #define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
7597 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
7598 #define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
7599 #define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
7600 #define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
7601 #define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
7603 #define FMC_BWTR3_ACCMOD_Pos (28U)
7604 #define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
7605 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
7606 #define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
7607 #define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
7609 /****************** Bit definition for FMC_BWTR4 register ******************/
7610 #define FMC_BWTR4_ADDSET_Pos (0U)
7611 #define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
7612 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
7613 #define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
7614 #define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
7615 #define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
7616 #define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
7618 #define FMC_BWTR4_ADDHLD_Pos (4U)
7619 #define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
7620 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
7621 #define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
7622 #define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
7623 #define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
7624 #define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
7626 #define FMC_BWTR4_DATAST_Pos (8U)
7627 #define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
7628 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
7629 #define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
7630 #define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
7631 #define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
7632 #define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
7633 #define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
7634 #define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
7635 #define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
7636 #define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
7638 #define FMC_BWTR4_BUSTURN_Pos (16U)
7639 #define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
7640 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
7641 #define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
7642 #define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
7643 #define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
7644 #define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
7646 #define FMC_BWTR4_ACCMOD_Pos (28U)
7647 #define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
7648 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
7649 #define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
7650 #define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
7652 /****************** Bit definition for FMC_PCR register *******************/
7653 #define FMC_PCR_PWAITEN_Pos (1U)
7654 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
7655 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
7656 #define FMC_PCR_PBKEN_Pos (2U)
7657 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
7658 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
7659 #define FMC_PCR_PTYP_Pos (3U)
7660 #define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
7661 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
7663 #define FMC_PCR_PWID_Pos (4U)
7664 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
7665 #define FMC_PCR_PWID FMC_PCR_PWID_Msk
7666 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
7667 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
7669 #define FMC_PCR_ECCEN_Pos (6U)
7670 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
7671 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
7673 #define FMC_PCR_TCLR_Pos (9U)
7674 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
7675 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
7676 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
7677 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
7678 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
7679 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
7681 #define FMC_PCR_TAR_Pos (13U)
7682 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
7683 #define FMC_PCR_TAR FMC_PCR_TAR_Msk
7684 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
7685 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
7686 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
7687 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
7689 #define FMC_PCR_ECCPS_Pos (17U)
7690 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
7691 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
7692 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
7693 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
7694 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
7696 /******************* Bit definition for FMC_SR register *******************/
7697 #define FMC_SR_IRS_Pos (0U)
7698 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
7699 #define FMC_SR_IRS FMC_SR_IRS_Msk
7700 #define FMC_SR_ILS_Pos (1U)
7701 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
7702 #define FMC_SR_ILS FMC_SR_ILS_Msk
7703 #define FMC_SR_IFS_Pos (2U)
7704 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
7705 #define FMC_SR_IFS FMC_SR_IFS_Msk
7706 #define FMC_SR_IREN_Pos (3U)
7707 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
7708 #define FMC_SR_IREN FMC_SR_IREN_Msk
7709 #define FMC_SR_ILEN_Pos (4U)
7710 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
7711 #define FMC_SR_ILEN FMC_SR_ILEN_Msk
7712 #define FMC_SR_IFEN_Pos (5U)
7713 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
7714 #define FMC_SR_IFEN FMC_SR_IFEN_Msk
7715 #define FMC_SR_FEMPT_Pos (6U)
7716 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
7717 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
7719 /****************** Bit definition for FMC_PMEM register ******************/
7720 #define FMC_PMEM_MEMSET2_Pos (0U)
7721 #define FMC_PMEM_MEMSET2_Msk (0xFFUL << FMC_PMEM_MEMSET2_Pos)
7722 #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk
7723 #define FMC_PMEM_MEMSET2_0 (0x01UL << FMC_PMEM_MEMSET2_Pos)
7724 #define FMC_PMEM_MEMSET2_1 (0x02UL << FMC_PMEM_MEMSET2_Pos)
7725 #define FMC_PMEM_MEMSET2_2 (0x04UL << FMC_PMEM_MEMSET2_Pos)
7726 #define FMC_PMEM_MEMSET2_3 (0x08UL << FMC_PMEM_MEMSET2_Pos)
7727 #define FMC_PMEM_MEMSET2_4 (0x10UL << FMC_PMEM_MEMSET2_Pos)
7728 #define FMC_PMEM_MEMSET2_5 (0x20UL << FMC_PMEM_MEMSET2_Pos)
7729 #define FMC_PMEM_MEMSET2_6 (0x40UL << FMC_PMEM_MEMSET2_Pos)
7730 #define FMC_PMEM_MEMSET2_7 (0x80UL << FMC_PMEM_MEMSET2_Pos)
7732 #define FMC_PMEM_MEMWAIT2_Pos (8U)
7733 #define FMC_PMEM_MEMWAIT2_Msk (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)
7734 #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk
7735 #define FMC_PMEM_MEMWAIT2_0 (0x01UL << FMC_PMEM_MEMWAIT2_Pos)
7736 #define FMC_PMEM_MEMWAIT2_1 (0x02UL << FMC_PMEM_MEMWAIT2_Pos)
7737 #define FMC_PMEM_MEMWAIT2_2 (0x04UL << FMC_PMEM_MEMWAIT2_Pos)
7738 #define FMC_PMEM_MEMWAIT2_3 (0x08UL << FMC_PMEM_MEMWAIT2_Pos)
7739 #define FMC_PMEM_MEMWAIT2_4 (0x10UL << FMC_PMEM_MEMWAIT2_Pos)
7740 #define FMC_PMEM_MEMWAIT2_5 (0x20UL << FMC_PMEM_MEMWAIT2_Pos)
7741 #define FMC_PMEM_MEMWAIT2_6 (0x40UL << FMC_PMEM_MEMWAIT2_Pos)
7742 #define FMC_PMEM_MEMWAIT2_7 (0x80UL << FMC_PMEM_MEMWAIT2_Pos)
7744 #define FMC_PMEM_MEMHOLD2_Pos (16U)
7745 #define FMC_PMEM_MEMHOLD2_Msk (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)
7746 #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk
7747 #define FMC_PMEM_MEMHOLD2_0 (0x01UL << FMC_PMEM_MEMHOLD2_Pos)
7748 #define FMC_PMEM_MEMHOLD2_1 (0x02UL << FMC_PMEM_MEMHOLD2_Pos)
7749 #define FMC_PMEM_MEMHOLD2_2 (0x04UL << FMC_PMEM_MEMHOLD2_Pos)
7750 #define FMC_PMEM_MEMHOLD2_3 (0x08UL << FMC_PMEM_MEMHOLD2_Pos)
7751 #define FMC_PMEM_MEMHOLD2_4 (0x10UL << FMC_PMEM_MEMHOLD2_Pos)
7752 #define FMC_PMEM_MEMHOLD2_5 (0x20UL << FMC_PMEM_MEMHOLD2_Pos)
7753 #define FMC_PMEM_MEMHOLD2_6 (0x40UL << FMC_PMEM_MEMHOLD2_Pos)
7754 #define FMC_PMEM_MEMHOLD2_7 (0x80UL << FMC_PMEM_MEMHOLD2_Pos)
7756 #define FMC_PMEM_MEMHIZ2_Pos (24U)
7757 #define FMC_PMEM_MEMHIZ2_Msk (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)
7758 #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk
7759 #define FMC_PMEM_MEMHIZ2_0 (0x01UL << FMC_PMEM_MEMHIZ2_Pos)
7760 #define FMC_PMEM_MEMHIZ2_1 (0x02UL << FMC_PMEM_MEMHIZ2_Pos)
7761 #define FMC_PMEM_MEMHIZ2_2 (0x04UL << FMC_PMEM_MEMHIZ2_Pos)
7762 #define FMC_PMEM_MEMHIZ2_3 (0x08UL << FMC_PMEM_MEMHIZ2_Pos)
7763 #define FMC_PMEM_MEMHIZ2_4 (0x10UL << FMC_PMEM_MEMHIZ2_Pos)
7764 #define FMC_PMEM_MEMHIZ2_5 (0x20UL << FMC_PMEM_MEMHIZ2_Pos)
7765 #define FMC_PMEM_MEMHIZ2_6 (0x40UL << FMC_PMEM_MEMHIZ2_Pos)
7766 #define FMC_PMEM_MEMHIZ2_7 (0x80UL << FMC_PMEM_MEMHIZ2_Pos)
7768 /****************** Bit definition for FMC_PATT register ******************/
7769 #define FMC_PATT_ATTSET2_Pos (0U)
7770 #define FMC_PATT_ATTSET2_Msk (0xFFUL << FMC_PATT_ATTSET2_Pos)
7771 #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk
7772 #define FMC_PATT_ATTSET2_0 (0x01UL << FMC_PATT_ATTSET2_Pos)
7773 #define FMC_PATT_ATTSET2_1 (0x02UL << FMC_PATT_ATTSET2_Pos)
7774 #define FMC_PATT_ATTSET2_2 (0x04UL << FMC_PATT_ATTSET2_Pos)
7775 #define FMC_PATT_ATTSET2_3 (0x08UL << FMC_PATT_ATTSET2_Pos)
7776 #define FMC_PATT_ATTSET2_4 (0x10UL << FMC_PATT_ATTSET2_Pos)
7777 #define FMC_PATT_ATTSET2_5 (0x20UL << FMC_PATT_ATTSET2_Pos)
7778 #define FMC_PATT_ATTSET2_6 (0x40UL << FMC_PATT_ATTSET2_Pos)
7779 #define FMC_PATT_ATTSET2_7 (0x80UL << FMC_PATT_ATTSET2_Pos)
7781 #define FMC_PATT_ATTWAIT2_Pos (8U)
7782 #define FMC_PATT_ATTWAIT2_Msk (0xFFUL << FMC_PATT_ATTWAIT2_Pos)
7783 #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk
7784 #define FMC_PATT_ATTWAIT2_0 (0x01UL << FMC_PATT_ATTWAIT2_Pos)
7785 #define FMC_PATT_ATTWAIT2_1 (0x02UL << FMC_PATT_ATTWAIT2_Pos)
7786 #define FMC_PATT_ATTWAIT2_2 (0x04UL << FMC_PATT_ATTWAIT2_Pos)
7787 #define FMC_PATT_ATTWAIT2_3 (0x08UL << FMC_PATT_ATTWAIT2_Pos)
7788 #define FMC_PATT_ATTWAIT2_4 (0x10UL << FMC_PATT_ATTWAIT2_Pos)
7789 #define FMC_PATT_ATTWAIT2_5 (0x20UL << FMC_PATT_ATTWAIT2_Pos)
7790 #define FMC_PATT_ATTWAIT2_6 (0x40UL << FMC_PATT_ATTWAIT2_Pos)
7791 #define FMC_PATT_ATTWAIT2_7 (0x80UL << FMC_PATT_ATTWAIT2_Pos)
7793 #define FMC_PATT_ATTHOLD2_Pos (16U)
7794 #define FMC_PATT_ATTHOLD2_Msk (0xFFUL << FMC_PATT_ATTHOLD2_Pos)
7795 #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk
7796 #define FMC_PATT_ATTHOLD2_0 (0x01UL << FMC_PATT_ATTHOLD2_Pos)
7797 #define FMC_PATT_ATTHOLD2_1 (0x02UL << FMC_PATT_ATTHOLD2_Pos)
7798 #define FMC_PATT_ATTHOLD2_2 (0x04UL << FMC_PATT_ATTHOLD2_Pos)
7799 #define FMC_PATT_ATTHOLD2_3 (0x08UL << FMC_PATT_ATTHOLD2_Pos)
7800 #define FMC_PATT_ATTHOLD2_4 (0x10UL << FMC_PATT_ATTHOLD2_Pos)
7801 #define FMC_PATT_ATTHOLD2_5 (0x20UL << FMC_PATT_ATTHOLD2_Pos)
7802 #define FMC_PATT_ATTHOLD2_6 (0x40UL << FMC_PATT_ATTHOLD2_Pos)
7803 #define FMC_PATT_ATTHOLD2_7 (0x80UL << FMC_PATT_ATTHOLD2_Pos)
7805 #define FMC_PATT_ATTHIZ2_Pos (24U)
7806 #define FMC_PATT_ATTHIZ2_Msk (0xFFUL << FMC_PATT_ATTHIZ2_Pos)
7807 #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk
7808 #define FMC_PATT_ATTHIZ2_0 (0x01UL << FMC_PATT_ATTHIZ2_Pos)
7809 #define FMC_PATT_ATTHIZ2_1 (0x02UL << FMC_PATT_ATTHIZ2_Pos)
7810 #define FMC_PATT_ATTHIZ2_2 (0x04UL << FMC_PATT_ATTHIZ2_Pos)
7811 #define FMC_PATT_ATTHIZ2_3 (0x08UL << FMC_PATT_ATTHIZ2_Pos)
7812 #define FMC_PATT_ATTHIZ2_4 (0x10UL << FMC_PATT_ATTHIZ2_Pos)
7813 #define FMC_PATT_ATTHIZ2_5 (0x20UL << FMC_PATT_ATTHIZ2_Pos)
7814 #define FMC_PATT_ATTHIZ2_6 (0x40UL << FMC_PATT_ATTHIZ2_Pos)
7815 #define FMC_PATT_ATTHIZ2_7 (0x80UL << FMC_PATT_ATTHIZ2_Pos)
7817 /****************** Bit definition for FMC_ECCR register ******************/
7818 #define FMC_ECCR_ECC2_Pos (0U)
7819 #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)
7820 #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk
7822 /****************** Bit definition for FMC_SDCR1 register ******************/
7823 #define FMC_SDCR1_NC_Pos (0U)
7824 #define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
7825 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
7826 #define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
7827 #define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
7829 #define FMC_SDCR1_NR_Pos (2U)
7830 #define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
7831 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
7832 #define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
7833 #define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
7835 #define FMC_SDCR1_MWID_Pos (4U)
7836 #define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
7837 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
7838 #define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
7839 #define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
7841 #define FMC_SDCR1_NB_Pos (6U)
7842 #define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
7843 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
7845 #define FMC_SDCR1_CAS_Pos (7U)
7846 #define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
7847 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
7848 #define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
7849 #define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
7851 #define FMC_SDCR1_WP_Pos (9U)
7852 #define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
7853 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
7855 #define FMC_SDCR1_SDCLK_Pos (10U)
7856 #define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
7857 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
7858 #define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
7859 #define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
7861 #define FMC_SDCR1_RBURST_Pos (12U)
7862 #define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
7863 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
7865 #define FMC_SDCR1_RPIPE_Pos (13U)
7866 #define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
7867 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
7868 #define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
7869 #define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
7871 /****************** Bit definition for FMC_SDCR2 register ******************/
7872 #define FMC_SDCR2_NC_Pos (0U)
7873 #define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
7874 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
7875 #define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
7876 #define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
7878 #define FMC_SDCR2_NR_Pos (2U)
7879 #define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
7880 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
7881 #define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
7882 #define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
7884 #define FMC_SDCR2_MWID_Pos (4U)
7885 #define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
7886 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
7887 #define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
7888 #define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
7890 #define FMC_SDCR2_NB_Pos (6U)
7891 #define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
7892 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
7894 #define FMC_SDCR2_CAS_Pos (7U)
7895 #define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
7896 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
7897 #define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
7898 #define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
7900 #define FMC_SDCR2_WP_Pos (9U)
7901 #define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
7902 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
7904 #define FMC_SDCR2_SDCLK_Pos (10U)
7905 #define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
7906 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
7907 #define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
7908 #define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
7910 #define FMC_SDCR2_RBURST_Pos (12U)
7911 #define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
7912 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
7914 #define FMC_SDCR2_RPIPE_Pos (13U)
7915 #define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
7916 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
7917 #define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
7918 #define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
7920 /****************** Bit definition for FMC_SDTR1 register ******************/
7921 #define FMC_SDTR1_TMRD_Pos (0U)
7922 #define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
7923 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
7924 #define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
7925 #define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
7926 #define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
7927 #define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
7929 #define FMC_SDTR1_TXSR_Pos (4U)
7930 #define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
7931 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
7932 #define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
7933 #define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
7934 #define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
7935 #define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
7937 #define FMC_SDTR1_TRAS_Pos (8U)
7938 #define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
7939 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
7940 #define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
7941 #define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
7942 #define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
7943 #define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
7945 #define FMC_SDTR1_TRC_Pos (12U)
7946 #define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
7947 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
7948 #define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
7949 #define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
7950 #define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
7952 #define FMC_SDTR1_TWR_Pos (16U)
7953 #define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
7954 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
7955 #define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
7956 #define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
7957 #define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
7959 #define FMC_SDTR1_TRP_Pos (20U)
7960 #define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
7961 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
7962 #define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
7963 #define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
7964 #define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
7966 #define FMC_SDTR1_TRCD_Pos (24U)
7967 #define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
7968 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
7969 #define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
7970 #define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
7971 #define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
7973 /****************** Bit definition for FMC_SDTR2 register ******************/
7974 #define FMC_SDTR2_TMRD_Pos (0U)
7975 #define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
7976 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
7977 #define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
7978 #define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
7979 #define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
7980 #define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
7982 #define FMC_SDTR2_TXSR_Pos (4U)
7983 #define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
7984 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
7985 #define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
7986 #define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
7987 #define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
7988 #define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
7990 #define FMC_SDTR2_TRAS_Pos (8U)
7991 #define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
7992 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
7993 #define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
7994 #define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
7995 #define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
7996 #define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
7998 #define FMC_SDTR2_TRC_Pos (12U)
7999 #define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
8000 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
8001 #define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
8002 #define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
8003 #define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
8005 #define FMC_SDTR2_TWR_Pos (16U)
8006 #define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
8007 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
8008 #define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
8009 #define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
8010 #define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
8012 #define FMC_SDTR2_TRP_Pos (20U)
8013 #define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
8014 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
8015 #define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
8016 #define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
8017 #define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
8019 #define FMC_SDTR2_TRCD_Pos (24U)
8020 #define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
8021 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
8022 #define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
8023 #define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
8024 #define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
8026 /****************** Bit definition for FMC_SDCMR register ******************/
8027 #define FMC_SDCMR_MODE_Pos (0U)
8028 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
8029 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
8030 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
8031 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
8032 #define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
8034 #define FMC_SDCMR_CTB2_Pos (3U)
8035 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
8036 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
8038 #define FMC_SDCMR_CTB1_Pos (4U)
8039 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
8040 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
8042 #define FMC_SDCMR_NRFS_Pos (5U)
8043 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
8044 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
8045 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
8046 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
8047 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
8048 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
8050 #define FMC_SDCMR_MRD_Pos (9U)
8051 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
8052 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
8054 /****************** Bit definition for FMC_SDRTR register ******************/
8055 #define FMC_SDRTR_CRE_Pos (0U)
8056 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
8057 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
8059 #define FMC_SDRTR_COUNT_Pos (1U)
8060 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
8061 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
8063 #define FMC_SDRTR_REIE_Pos (14U)
8064 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
8065 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
8067 /****************** Bit definition for FMC_SDSR register ******************/
8068 #define FMC_SDSR_RE_Pos (0U)
8069 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
8070 #define FMC_SDSR_RE FMC_SDSR_RE_Msk
8072 #define FMC_SDSR_MODES1_Pos (1U)
8073 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
8074 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
8075 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
8076 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
8078 #define FMC_SDSR_MODES2_Pos (3U)
8079 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
8080 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
8081 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
8082 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
8083 #define FMC_SDSR_BUSY_Pos (5U)
8084 #define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
8085 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
8087 /******************************************************************************/
8088 /* */
8089 /* General Purpose I/O */
8090 /* */
8091 /******************************************************************************/
8092 /****************** Bits definition for GPIO_MODER register *****************/
8093 #define GPIO_MODER_MODER0_Pos (0U)
8094 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8095 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8096 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8097 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8098 #define GPIO_MODER_MODER1_Pos (2U)
8099 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8100 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8101 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8102 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8103 #define GPIO_MODER_MODER2_Pos (4U)
8104 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8105 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8106 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8107 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8108 #define GPIO_MODER_MODER3_Pos (6U)
8109 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8110 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8111 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8112 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8113 #define GPIO_MODER_MODER4_Pos (8U)
8114 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8115 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8116 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8117 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8118 #define GPIO_MODER_MODER5_Pos (10U)
8119 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8120 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8121 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8122 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8123 #define GPIO_MODER_MODER6_Pos (12U)
8124 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8125 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8126 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8127 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8128 #define GPIO_MODER_MODER7_Pos (14U)
8129 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8130 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8131 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8132 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8133 #define GPIO_MODER_MODER8_Pos (16U)
8134 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8135 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8136 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8137 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8138 #define GPIO_MODER_MODER9_Pos (18U)
8139 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8140 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8141 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8142 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8143 #define GPIO_MODER_MODER10_Pos (20U)
8144 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8145 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8146 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8147 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8148 #define GPIO_MODER_MODER11_Pos (22U)
8149 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8150 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8151 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8152 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8153 #define GPIO_MODER_MODER12_Pos (24U)
8154 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8155 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8156 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8157 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8158 #define GPIO_MODER_MODER13_Pos (26U)
8159 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8160 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8161 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8162 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8163 #define GPIO_MODER_MODER14_Pos (28U)
8164 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8165 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8166 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8167 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8168 #define GPIO_MODER_MODER15_Pos (30U)
8169 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8170 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8171 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8172 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8174 /* Legacy defines */
8175 #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
8176 #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
8177 #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
8178 #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
8179 #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
8180 #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
8181 #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
8182 #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
8183 #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
8184 #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
8185 #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
8186 #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
8187 #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
8188 #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
8189 #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
8190 #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
8191 #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
8192 #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
8193 #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
8194 #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
8195 #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
8196 #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
8197 #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
8198 #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
8199 #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
8200 #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
8201 #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
8202 #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
8203 #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
8204 #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
8205 #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
8206 #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
8207 #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
8208 #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
8209 #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
8210 #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
8211 #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
8212 #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
8213 #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
8214 #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
8215 #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
8216 #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
8217 #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
8218 #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
8219 #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
8220 #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
8221 #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
8222 #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
8223 #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
8224 #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
8225 #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
8226 #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
8227 #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
8228 #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
8229 #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
8230 #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
8231 #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
8232 #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
8233 #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
8234 #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
8235 #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
8236 #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
8237 #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
8238 #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
8239 #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
8240 #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
8241 #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
8242 #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
8243 #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
8244 #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
8245 #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
8246 #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
8247 #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
8248 #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
8249 #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
8250 #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
8251 #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
8252 #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
8253 #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
8254 #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
8255 
8256 /****************** Bits definition for GPIO_OTYPER register ****************/
8257 #define GPIO_OTYPER_OT0_Pos (0U)
8258 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8259 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8260 #define GPIO_OTYPER_OT1_Pos (1U)
8261 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8262 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8263 #define GPIO_OTYPER_OT2_Pos (2U)
8264 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8265 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8266 #define GPIO_OTYPER_OT3_Pos (3U)
8267 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8268 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8269 #define GPIO_OTYPER_OT4_Pos (4U)
8270 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8271 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8272 #define GPIO_OTYPER_OT5_Pos (5U)
8273 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8274 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8275 #define GPIO_OTYPER_OT6_Pos (6U)
8276 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8277 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8278 #define GPIO_OTYPER_OT7_Pos (7U)
8279 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8280 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8281 #define GPIO_OTYPER_OT8_Pos (8U)
8282 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8283 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8284 #define GPIO_OTYPER_OT9_Pos (9U)
8285 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8286 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8287 #define GPIO_OTYPER_OT10_Pos (10U)
8288 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8289 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8290 #define GPIO_OTYPER_OT11_Pos (11U)
8291 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8292 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8293 #define GPIO_OTYPER_OT12_Pos (12U)
8294 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8295 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8296 #define GPIO_OTYPER_OT13_Pos (13U)
8297 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8298 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8299 #define GPIO_OTYPER_OT14_Pos (14U)
8300 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8301 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8302 #define GPIO_OTYPER_OT15_Pos (15U)
8303 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8304 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8305 
8306 /* Legacy defines */
8307 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8308 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8309 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8310 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8311 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8312 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8313 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8314 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8315 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8316 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8317 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8318 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8319 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8320 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8321 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8322 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8323 
8324 /****************** Bits definition for GPIO_OSPEEDR register ***************/
8325 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8326 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
8327 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8328 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
8329 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
8330 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8331 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
8332 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8333 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
8334 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
8335 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8336 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
8337 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8338 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
8339 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
8340 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8341 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
8342 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8343 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
8344 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
8345 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8346 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
8347 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8348 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
8349 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
8350 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8351 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
8352 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8353 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
8354 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
8355 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8356 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
8357 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8358 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
8359 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
8360 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8361 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
8362 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8363 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
8364 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
8365 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8366 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
8367 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8368 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
8369 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
8370 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8371 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
8372 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8373 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
8374 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
8375 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8376 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
8377 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8378 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
8379 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
8380 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8381 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
8382 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8383 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
8384 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
8385 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8386 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
8387 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8388 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
8389 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
8390 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8391 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
8392 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8393 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
8394 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
8395 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8396 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
8397 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8398 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
8399 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
8400 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8401 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
8402 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8403 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
8404 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
8406 /* Legacy defines */
8407 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8408 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8409 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8410 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8411 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8412 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8413 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8414 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8415 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8416 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8417 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8418 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8419 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8420 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8421 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8422 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8423 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8424 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8425 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8426 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8427 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8428 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8429 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8430 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8431 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8432 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8433 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8434 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8435 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8436 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8437 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8438 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8439 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8440 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8441 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8442 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8443 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8444 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8445 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8446 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8447 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8448 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8449 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8450 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8451 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8452 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8453 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8454 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8455 
8456 /****************** Bits definition for GPIO_PUPDR register *****************/
8457 #define GPIO_PUPDR_PUPD0_Pos (0U)
8458 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
8459 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8460 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
8461 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
8462 #define GPIO_PUPDR_PUPD1_Pos (2U)
8463 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
8464 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8465 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
8466 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
8467 #define GPIO_PUPDR_PUPD2_Pos (4U)
8468 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
8469 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8470 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
8471 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
8472 #define GPIO_PUPDR_PUPD3_Pos (6U)
8473 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
8474 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8475 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
8476 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
8477 #define GPIO_PUPDR_PUPD4_Pos (8U)
8478 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
8479 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8480 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
8481 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
8482 #define GPIO_PUPDR_PUPD5_Pos (10U)
8483 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
8484 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8485 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
8486 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
8487 #define GPIO_PUPDR_PUPD6_Pos (12U)
8488 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
8489 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8490 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
8491 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
8492 #define GPIO_PUPDR_PUPD7_Pos (14U)
8493 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
8494 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8495 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
8496 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
8497 #define GPIO_PUPDR_PUPD8_Pos (16U)
8498 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
8499 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8500 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
8501 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
8502 #define GPIO_PUPDR_PUPD9_Pos (18U)
8503 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
8504 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8505 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8506 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8507 #define GPIO_PUPDR_PUPD10_Pos (20U)
8508 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8509 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8510 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8511 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8512 #define GPIO_PUPDR_PUPD11_Pos (22U)
8513 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8514 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8515 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8516 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8517 #define GPIO_PUPDR_PUPD12_Pos (24U)
8518 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8519 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8520 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8521 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8522 #define GPIO_PUPDR_PUPD13_Pos (26U)
8523 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8524 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8525 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8526 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8527 #define GPIO_PUPDR_PUPD14_Pos (28U)
8528 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8529 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8530 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8531 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8532 #define GPIO_PUPDR_PUPD15_Pos (30U)
8533 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8534 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8535 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8536 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8538 /* Legacy defines */
8539 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8540 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8541 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8542 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8543 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8544 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8545 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8546 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8547 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8548 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8549 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8550 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8551 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8552 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8553 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8554 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8555 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8556 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8557 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8558 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8559 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8560 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8561 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8562 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8563 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8564 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8565 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8566 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8567 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8568 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8569 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8570 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8571 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8572 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8573 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8574 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8575 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8576 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8577 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8578 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8579 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8580 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8581 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8582 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8583 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8584 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8585 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8586 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8587 
8588 /****************** Bits definition for GPIO_IDR register *******************/
8589 #define GPIO_IDR_ID0_Pos (0U)
8590 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8591 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8592 #define GPIO_IDR_ID1_Pos (1U)
8593 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8594 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8595 #define GPIO_IDR_ID2_Pos (2U)
8596 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8597 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8598 #define GPIO_IDR_ID3_Pos (3U)
8599 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8600 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8601 #define GPIO_IDR_ID4_Pos (4U)
8602 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8603 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8604 #define GPIO_IDR_ID5_Pos (5U)
8605 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8606 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8607 #define GPIO_IDR_ID6_Pos (6U)
8608 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8609 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8610 #define GPIO_IDR_ID7_Pos (7U)
8611 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8612 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8613 #define GPIO_IDR_ID8_Pos (8U)
8614 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8615 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8616 #define GPIO_IDR_ID9_Pos (9U)
8617 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8618 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8619 #define GPIO_IDR_ID10_Pos (10U)
8620 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8621 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8622 #define GPIO_IDR_ID11_Pos (11U)
8623 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8624 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8625 #define GPIO_IDR_ID12_Pos (12U)
8626 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8627 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8628 #define GPIO_IDR_ID13_Pos (13U)
8629 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8630 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8631 #define GPIO_IDR_ID14_Pos (14U)
8632 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8633 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8634 #define GPIO_IDR_ID15_Pos (15U)
8635 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8636 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8637 
8638 /* Legacy defines */
8639 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8640 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8641 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8642 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8643 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8644 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8645 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8646 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8647 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8648 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8649 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8650 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8651 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8652 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8653 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8654 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8655 
8656 /****************** Bits definition for GPIO_ODR register *******************/
8657 #define GPIO_ODR_OD0_Pos (0U)
8658 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8659 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8660 #define GPIO_ODR_OD1_Pos (1U)
8661 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8662 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8663 #define GPIO_ODR_OD2_Pos (2U)
8664 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8665 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8666 #define GPIO_ODR_OD3_Pos (3U)
8667 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8668 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8669 #define GPIO_ODR_OD4_Pos (4U)
8670 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8671 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8672 #define GPIO_ODR_OD5_Pos (5U)
8673 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8674 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8675 #define GPIO_ODR_OD6_Pos (6U)
8676 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8677 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8678 #define GPIO_ODR_OD7_Pos (7U)
8679 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8680 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8681 #define GPIO_ODR_OD8_Pos (8U)
8682 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8683 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8684 #define GPIO_ODR_OD9_Pos (9U)
8685 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8686 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8687 #define GPIO_ODR_OD10_Pos (10U)
8688 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8689 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8690 #define GPIO_ODR_OD11_Pos (11U)
8691 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8692 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8693 #define GPIO_ODR_OD12_Pos (12U)
8694 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8695 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8696 #define GPIO_ODR_OD13_Pos (13U)
8697 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8698 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8699 #define GPIO_ODR_OD14_Pos (14U)
8700 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8701 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8702 #define GPIO_ODR_OD15_Pos (15U)
8703 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8704 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8705 /* Legacy defines */
8706 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8707 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8708 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8709 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8710 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8711 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8712 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8713 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8714 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8715 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8716 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8717 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8718 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8719 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8720 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8721 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8722 
8723 /****************** Bits definition for GPIO_BSRR register ******************/
8724 #define GPIO_BSRR_BS0_Pos (0U)
8725 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8726 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8727 #define GPIO_BSRR_BS1_Pos (1U)
8728 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8729 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8730 #define GPIO_BSRR_BS2_Pos (2U)
8731 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8732 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8733 #define GPIO_BSRR_BS3_Pos (3U)
8734 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8735 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8736 #define GPIO_BSRR_BS4_Pos (4U)
8737 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8738 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8739 #define GPIO_BSRR_BS5_Pos (5U)
8740 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8741 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8742 #define GPIO_BSRR_BS6_Pos (6U)
8743 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8744 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8745 #define GPIO_BSRR_BS7_Pos (7U)
8746 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8747 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8748 #define GPIO_BSRR_BS8_Pos (8U)
8749 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8750 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8751 #define GPIO_BSRR_BS9_Pos (9U)
8752 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8753 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8754 #define GPIO_BSRR_BS10_Pos (10U)
8755 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8756 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8757 #define GPIO_BSRR_BS11_Pos (11U)
8758 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8759 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8760 #define GPIO_BSRR_BS12_Pos (12U)
8761 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8762 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8763 #define GPIO_BSRR_BS13_Pos (13U)
8764 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8765 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8766 #define GPIO_BSRR_BS14_Pos (14U)
8767 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8768 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8769 #define GPIO_BSRR_BS15_Pos (15U)
8770 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8771 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8772 #define GPIO_BSRR_BR0_Pos (16U)
8773 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8774 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8775 #define GPIO_BSRR_BR1_Pos (17U)
8776 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8777 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8778 #define GPIO_BSRR_BR2_Pos (18U)
8779 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8780 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8781 #define GPIO_BSRR_BR3_Pos (19U)
8782 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8783 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8784 #define GPIO_BSRR_BR4_Pos (20U)
8785 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8786 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8787 #define GPIO_BSRR_BR5_Pos (21U)
8788 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8789 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8790 #define GPIO_BSRR_BR6_Pos (22U)
8791 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8792 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8793 #define GPIO_BSRR_BR7_Pos (23U)
8794 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8795 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8796 #define GPIO_BSRR_BR8_Pos (24U)
8797 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8798 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8799 #define GPIO_BSRR_BR9_Pos (25U)
8800 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8801 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8802 #define GPIO_BSRR_BR10_Pos (26U)
8803 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8804 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8805 #define GPIO_BSRR_BR11_Pos (27U)
8806 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8807 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8808 #define GPIO_BSRR_BR12_Pos (28U)
8809 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8810 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8811 #define GPIO_BSRR_BR13_Pos (29U)
8812 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8813 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8814 #define GPIO_BSRR_BR14_Pos (30U)
8815 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8816 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8817 #define GPIO_BSRR_BR15_Pos (31U)
8818 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8819 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8820 
8821 /* Legacy defines */
8822 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8823 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8824 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8825 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8826 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8827 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8828 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8829 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8830 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8831 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8832 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8833 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8834 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8835 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8836 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8837 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8838 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8839 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8840 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8841 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8842 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8843 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8844 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8845 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8846 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8847 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8848 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8849 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8850 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8851 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8852 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8853 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8854 #define GPIO_BRR_BR0 GPIO_BSRR_BR0
8855 #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8856 #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8857 #define GPIO_BRR_BR1 GPIO_BSRR_BR1
8858 #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8859 #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8860 #define GPIO_BRR_BR2 GPIO_BSRR_BR2
8861 #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8862 #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8863 #define GPIO_BRR_BR3 GPIO_BSRR_BR3
8864 #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8865 #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8866 #define GPIO_BRR_BR4 GPIO_BSRR_BR4
8867 #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8868 #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8869 #define GPIO_BRR_BR5 GPIO_BSRR_BR5
8870 #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8871 #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8872 #define GPIO_BRR_BR6 GPIO_BSRR_BR6
8873 #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8874 #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8875 #define GPIO_BRR_BR7 GPIO_BSRR_BR7
8876 #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8877 #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8878 #define GPIO_BRR_BR8 GPIO_BSRR_BR8
8879 #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8880 #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8881 #define GPIO_BRR_BR9 GPIO_BSRR_BR9
8882 #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8883 #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8884 #define GPIO_BRR_BR10 GPIO_BSRR_BR10
8885 #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8886 #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8887 #define GPIO_BRR_BR11 GPIO_BSRR_BR11
8888 #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8889 #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8890 #define GPIO_BRR_BR12 GPIO_BSRR_BR12
8891 #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8892 #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8893 #define GPIO_BRR_BR13 GPIO_BSRR_BR13
8894 #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8895 #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8896 #define GPIO_BRR_BR14 GPIO_BSRR_BR14
8897 #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8898 #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8899 #define GPIO_BRR_BR15 GPIO_BSRR_BR15
8900 #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8901 #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8902 /****************** Bit definition for GPIO_LCKR register *********************/
8903 #define GPIO_LCKR_LCK0_Pos (0U)
8904 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8905 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8906 #define GPIO_LCKR_LCK1_Pos (1U)
8907 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8908 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8909 #define GPIO_LCKR_LCK2_Pos (2U)
8910 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8911 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8912 #define GPIO_LCKR_LCK3_Pos (3U)
8913 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8914 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8915 #define GPIO_LCKR_LCK4_Pos (4U)
8916 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8917 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8918 #define GPIO_LCKR_LCK5_Pos (5U)
8919 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8920 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8921 #define GPIO_LCKR_LCK6_Pos (6U)
8922 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8923 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8924 #define GPIO_LCKR_LCK7_Pos (7U)
8925 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8926 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8927 #define GPIO_LCKR_LCK8_Pos (8U)
8928 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8929 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8930 #define GPIO_LCKR_LCK9_Pos (9U)
8931 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8932 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8933 #define GPIO_LCKR_LCK10_Pos (10U)
8934 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8935 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8936 #define GPIO_LCKR_LCK11_Pos (11U)
8937 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8938 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8939 #define GPIO_LCKR_LCK12_Pos (12U)
8940 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8941 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8942 #define GPIO_LCKR_LCK13_Pos (13U)
8943 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8944 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8945 #define GPIO_LCKR_LCK14_Pos (14U)
8946 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8947 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8948 #define GPIO_LCKR_LCK15_Pos (15U)
8949 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8950 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8951 #define GPIO_LCKR_LCKK_Pos (16U)
8952 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8953 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8954 /****************** Bit definition for GPIO_AFRL register *********************/
8955 #define GPIO_AFRL_AFSEL0_Pos (0U)
8956 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8957 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8958 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8959 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8960 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8961 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8962 #define GPIO_AFRL_AFSEL1_Pos (4U)
8963 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8964 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8965 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8966 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8967 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8968 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8969 #define GPIO_AFRL_AFSEL2_Pos (8U)
8970 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8971 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8972 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8973 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8974 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8975 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8976 #define GPIO_AFRL_AFSEL3_Pos (12U)
8977 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8978 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8979 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8980 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8981 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8982 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8983 #define GPIO_AFRL_AFSEL4_Pos (16U)
8984 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8985 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8986 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8987 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8988 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8989 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8990 #define GPIO_AFRL_AFSEL5_Pos (20U)
8991 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8992 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8993 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8994 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8995 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8996 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8997 #define GPIO_AFRL_AFSEL6_Pos (24U)
8998 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8999 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
9000 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
9001 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
9002 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
9003 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
9004 #define GPIO_AFRL_AFSEL7_Pos (28U)
9005 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
9006 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
9007 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
9008 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
9009 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
9010 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
9012 /* Legacy defines */
9013 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
9014 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
9015 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
9016 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
9017 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
9018 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
9019 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
9020 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
9021 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
9022 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
9023 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
9024 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
9025 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
9026 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
9027 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
9028 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
9029 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
9030 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
9031 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
9032 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
9033 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
9034 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
9035 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
9036 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
9037 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
9038 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
9039 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
9040 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
9041 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
9042 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
9043 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9044 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
9045 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
9046 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
9047 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
9048 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9049 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9050 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9051 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9052 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9053 
9054 /****************** Bit definition for GPIO_AFRH register *********************/
9055 #define GPIO_AFRH_AFSEL8_Pos (0U)
9056 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
9057 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9058 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
9059 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
9060 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
9061 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
9062 #define GPIO_AFRH_AFSEL9_Pos (4U)
9063 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
9064 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9065 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
9066 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
9067 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
9068 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
9069 #define GPIO_AFRH_AFSEL10_Pos (8U)
9070 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
9071 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9072 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
9073 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
9074 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
9075 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
9076 #define GPIO_AFRH_AFSEL11_Pos (12U)
9077 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
9078 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9079 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
9080 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
9081 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
9082 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
9083 #define GPIO_AFRH_AFSEL12_Pos (16U)
9084 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
9085 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9086 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
9087 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
9088 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
9089 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
9090 #define GPIO_AFRH_AFSEL13_Pos (20U)
9091 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
9092 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9093 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
9094 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
9095 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
9096 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
9097 #define GPIO_AFRH_AFSEL14_Pos (24U)
9098 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
9099 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9100 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
9101 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
9102 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
9103 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
9104 #define GPIO_AFRH_AFSEL15_Pos (28U)
9105 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
9106 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9107 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
9108 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
9109 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
9110 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
9112 /* Legacy defines */
9113 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9114 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9115 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9116 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9117 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9118 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9119 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9120 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9121 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9122 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9123 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9124 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9125 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9126 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9127 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9128 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9129 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9130 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9131 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9132 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9133 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9134 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9135 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9136 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9137 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9138 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9139 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9140 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9141 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9142 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9143 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9144 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9145 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9146 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9147 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9148 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9149 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9150 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9151 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9152 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9153 
9154 
9155 /******************************************************************************/
9156 /* */
9157 /* Inter-integrated Circuit Interface */
9158 /* */
9159 /******************************************************************************/
9160 /******************* Bit definition for I2C_CR1 register ********************/
9161 #define I2C_CR1_PE_Pos (0U)
9162 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9163 #define I2C_CR1_PE I2C_CR1_PE_Msk
9164 #define I2C_CR1_SMBUS_Pos (1U)
9165 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
9166 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
9167 #define I2C_CR1_SMBTYPE_Pos (3U)
9168 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
9169 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
9170 #define I2C_CR1_ENARP_Pos (4U)
9171 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
9172 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
9173 #define I2C_CR1_ENPEC_Pos (5U)
9174 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
9175 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
9176 #define I2C_CR1_ENGC_Pos (6U)
9177 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
9178 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
9179 #define I2C_CR1_NOSTRETCH_Pos (7U)
9180 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9181 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9182 #define I2C_CR1_START_Pos (8U)
9183 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
9184 #define I2C_CR1_START I2C_CR1_START_Msk
9185 #define I2C_CR1_STOP_Pos (9U)
9186 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
9187 #define I2C_CR1_STOP I2C_CR1_STOP_Msk
9188 #define I2C_CR1_ACK_Pos (10U)
9189 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
9190 #define I2C_CR1_ACK I2C_CR1_ACK_Msk
9191 #define I2C_CR1_POS_Pos (11U)
9192 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
9193 #define I2C_CR1_POS I2C_CR1_POS_Msk
9194 #define I2C_CR1_PEC_Pos (12U)
9195 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
9196 #define I2C_CR1_PEC I2C_CR1_PEC_Msk
9197 #define I2C_CR1_ALERT_Pos (13U)
9198 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
9199 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
9200 #define I2C_CR1_SWRST_Pos (15U)
9201 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9202 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9204 /******************* Bit definition for I2C_CR2 register ********************/
9205 #define I2C_CR2_FREQ_Pos (0U)
9206 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
9207 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
9208 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
9209 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
9210 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
9211 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
9212 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
9213 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
9215 #define I2C_CR2_ITERREN_Pos (8U)
9216 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
9217 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
9218 #define I2C_CR2_ITEVTEN_Pos (9U)
9219 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
9220 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
9221 #define I2C_CR2_ITBUFEN_Pos (10U)
9222 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
9223 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
9224 #define I2C_CR2_DMAEN_Pos (11U)
9225 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
9226 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
9227 #define I2C_CR2_LAST_Pos (12U)
9228 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
9229 #define I2C_CR2_LAST I2C_CR2_LAST_Msk
9231 /******************* Bit definition for I2C_OAR1 register *******************/
9232 #define I2C_OAR1_ADD1_7 0x000000FEU
9233 #define I2C_OAR1_ADD8_9 0x00000300U
9235 #define I2C_OAR1_ADD0_Pos (0U)
9236 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
9237 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
9238 #define I2C_OAR1_ADD1_Pos (1U)
9239 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
9240 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
9241 #define I2C_OAR1_ADD2_Pos (2U)
9242 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
9243 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
9244 #define I2C_OAR1_ADD3_Pos (3U)
9245 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
9246 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
9247 #define I2C_OAR1_ADD4_Pos (4U)
9248 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
9249 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
9250 #define I2C_OAR1_ADD5_Pos (5U)
9251 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
9252 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
9253 #define I2C_OAR1_ADD6_Pos (6U)
9254 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
9255 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
9256 #define I2C_OAR1_ADD7_Pos (7U)
9257 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
9258 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
9259 #define I2C_OAR1_ADD8_Pos (8U)
9260 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
9261 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
9262 #define I2C_OAR1_ADD9_Pos (9U)
9263 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
9264 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
9266 #define I2C_OAR1_ADDMODE_Pos (15U)
9267 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
9268 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
9270 /******************* Bit definition for I2C_OAR2 register *******************/
9271 #define I2C_OAR2_ENDUAL_Pos (0U)
9272 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
9273 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
9274 #define I2C_OAR2_ADD2_Pos (1U)
9275 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
9276 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
9278 /******************** Bit definition for I2C_DR register ********************/
9279 #define I2C_DR_DR_Pos (0U)
9280 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
9281 #define I2C_DR_DR I2C_DR_DR_Msk
9283 /******************* Bit definition for I2C_SR1 register ********************/
9284 #define I2C_SR1_SB_Pos (0U)
9285 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
9286 #define I2C_SR1_SB I2C_SR1_SB_Msk
9287 #define I2C_SR1_ADDR_Pos (1U)
9288 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
9289 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
9290 #define I2C_SR1_BTF_Pos (2U)
9291 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
9292 #define I2C_SR1_BTF I2C_SR1_BTF_Msk
9293 #define I2C_SR1_ADD10_Pos (3U)
9294 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
9295 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
9296 #define I2C_SR1_STOPF_Pos (4U)
9297 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
9298 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
9299 #define I2C_SR1_RXNE_Pos (6U)
9300 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
9301 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
9302 #define I2C_SR1_TXE_Pos (7U)
9303 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
9304 #define I2C_SR1_TXE I2C_SR1_TXE_Msk
9305 #define I2C_SR1_BERR_Pos (8U)
9306 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
9307 #define I2C_SR1_BERR I2C_SR1_BERR_Msk
9308 #define I2C_SR1_ARLO_Pos (9U)
9309 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
9310 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
9311 #define I2C_SR1_AF_Pos (10U)
9312 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
9313 #define I2C_SR1_AF I2C_SR1_AF_Msk
9314 #define I2C_SR1_OVR_Pos (11U)
9315 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
9316 #define I2C_SR1_OVR I2C_SR1_OVR_Msk
9317 #define I2C_SR1_PECERR_Pos (12U)
9318 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
9319 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
9320 #define I2C_SR1_TIMEOUT_Pos (14U)
9321 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
9322 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
9323 #define I2C_SR1_SMBALERT_Pos (15U)
9324 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
9325 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
9327 /******************* Bit definition for I2C_SR2 register ********************/
9328 #define I2C_SR2_MSL_Pos (0U)
9329 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
9330 #define I2C_SR2_MSL I2C_SR2_MSL_Msk
9331 #define I2C_SR2_BUSY_Pos (1U)
9332 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
9333 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
9334 #define I2C_SR2_TRA_Pos (2U)
9335 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
9336 #define I2C_SR2_TRA I2C_SR2_TRA_Msk
9337 #define I2C_SR2_GENCALL_Pos (4U)
9338 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
9339 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
9340 #define I2C_SR2_SMBDEFAULT_Pos (5U)
9341 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
9342 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
9343 #define I2C_SR2_SMBHOST_Pos (6U)
9344 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
9345 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
9346 #define I2C_SR2_DUALF_Pos (7U)
9347 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
9348 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
9349 #define I2C_SR2_PEC_Pos (8U)
9350 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
9351 #define I2C_SR2_PEC I2C_SR2_PEC_Msk
9353 /******************* Bit definition for I2C_CCR register ********************/
9354 #define I2C_CCR_CCR_Pos (0U)
9355 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
9356 #define I2C_CCR_CCR I2C_CCR_CCR_Msk
9357 #define I2C_CCR_DUTY_Pos (14U)
9358 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
9359 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
9360 #define I2C_CCR_FS_Pos (15U)
9361 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
9362 #define I2C_CCR_FS I2C_CCR_FS_Msk
9364 /****************** Bit definition for I2C_TRISE register *******************/
9365 #define I2C_TRISE_TRISE_Pos (0U)
9366 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
9367 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
9369 /****************** Bit definition for I2C_FLTR register *******************/
9370 #define I2C_FLTR_DNF_Pos (0U)
9371 #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
9372 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
9373 #define I2C_FLTR_ANOFF_Pos (4U)
9374 #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
9375 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
9377 /******************************************************************************/
9378 /* */
9379 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
9380 /* */
9381 /******************************************************************************/
9382 /******************* Bit definition for I2C_CR1 register *******************/
9383 #define FMPI2C_CR1_PE_Pos (0U)
9384 #define FMPI2C_CR1_PE_Msk (0x1UL << FMPI2C_CR1_PE_Pos)
9385 #define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk
9386 #define FMPI2C_CR1_TXIE_Pos (1U)
9387 #define FMPI2C_CR1_TXIE_Msk (0x1UL << FMPI2C_CR1_TXIE_Pos)
9388 #define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk
9389 #define FMPI2C_CR1_RXIE_Pos (2U)
9390 #define FMPI2C_CR1_RXIE_Msk (0x1UL << FMPI2C_CR1_RXIE_Pos)
9391 #define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk
9392 #define FMPI2C_CR1_ADDRIE_Pos (3U)
9393 #define FMPI2C_CR1_ADDRIE_Msk (0x1UL << FMPI2C_CR1_ADDRIE_Pos)
9394 #define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk
9395 #define FMPI2C_CR1_NACKIE_Pos (4U)
9396 #define FMPI2C_CR1_NACKIE_Msk (0x1UL << FMPI2C_CR1_NACKIE_Pos)
9397 #define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk
9398 #define FMPI2C_CR1_STOPIE_Pos (5U)
9399 #define FMPI2C_CR1_STOPIE_Msk (0x1UL << FMPI2C_CR1_STOPIE_Pos)
9400 #define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk
9401 #define FMPI2C_CR1_TCIE_Pos (6U)
9402 #define FMPI2C_CR1_TCIE_Msk (0x1UL << FMPI2C_CR1_TCIE_Pos)
9403 #define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk
9404 #define FMPI2C_CR1_ERRIE_Pos (7U)
9405 #define FMPI2C_CR1_ERRIE_Msk (0x1UL << FMPI2C_CR1_ERRIE_Pos)
9406 #define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk
9407 #define FMPI2C_CR1_DNF_Pos (8U)
9408 #define FMPI2C_CR1_DNF_Msk (0xFUL << FMPI2C_CR1_DNF_Pos)
9409 #define FMPI2C_CR1_DNF FMPI2C_CR1_DNF_Msk
9410 #define FMPI2C_CR1_ANFOFF_Pos (12U)
9411 #define FMPI2C_CR1_ANFOFF_Msk (0x1UL << FMPI2C_CR1_ANFOFF_Pos)
9412 #define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk
9413 #define FMPI2C_CR1_TXDMAEN_Pos (14U)
9414 #define FMPI2C_CR1_TXDMAEN_Msk (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)
9415 #define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk
9416 #define FMPI2C_CR1_RXDMAEN_Pos (15U)
9417 #define FMPI2C_CR1_RXDMAEN_Msk (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)
9418 #define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk
9419 #define FMPI2C_CR1_SBC_Pos (16U)
9420 #define FMPI2C_CR1_SBC_Msk (0x1UL << FMPI2C_CR1_SBC_Pos)
9421 #define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk
9422 #define FMPI2C_CR1_NOSTRETCH_Pos (17U)
9423 #define FMPI2C_CR1_NOSTRETCH_Msk (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)
9424 #define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk
9425 #define FMPI2C_CR1_GCEN_Pos (19U)
9426 #define FMPI2C_CR1_GCEN_Msk (0x1UL << FMPI2C_CR1_GCEN_Pos)
9427 #define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk
9428 #define FMPI2C_CR1_SMBHEN_Pos (20U)
9429 #define FMPI2C_CR1_SMBHEN_Msk (0x1UL << FMPI2C_CR1_SMBHEN_Pos)
9430 #define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk
9431 #define FMPI2C_CR1_SMBDEN_Pos (21U)
9432 #define FMPI2C_CR1_SMBDEN_Msk (0x1UL << FMPI2C_CR1_SMBDEN_Pos)
9433 #define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk
9434 #define FMPI2C_CR1_ALERTEN_Pos (22U)
9435 #define FMPI2C_CR1_ALERTEN_Msk (0x1UL << FMPI2C_CR1_ALERTEN_Pos)
9436 #define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk
9437 #define FMPI2C_CR1_PECEN_Pos (23U)
9438 #define FMPI2C_CR1_PECEN_Msk (0x1UL << FMPI2C_CR1_PECEN_Pos)
9439 #define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk
9441 /* Legacy Defines */
9442 #define FMPI2C_CR1_DFN_Pos FMPI2C_CR1_DNF_Pos
9443 #define FMPI2C_CR1_DFN_Msk FMPI2C_CR1_DNF_Msk
9444 #define FMPI2C_CR1_DFN FMPI2C_CR1_DNF
9445 /****************** Bit definition for I2C_CR2 register ********************/
9446 #define FMPI2C_CR2_SADD_Pos (0U)
9447 #define FMPI2C_CR2_SADD_Msk (0x3FFUL << FMPI2C_CR2_SADD_Pos)
9448 #define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk
9449 #define FMPI2C_CR2_RD_WRN_Pos (10U)
9450 #define FMPI2C_CR2_RD_WRN_Msk (0x1UL << FMPI2C_CR2_RD_WRN_Pos)
9451 #define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk
9452 #define FMPI2C_CR2_ADD10_Pos (11U)
9453 #define FMPI2C_CR2_ADD10_Msk (0x1UL << FMPI2C_CR2_ADD10_Pos)
9454 #define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk
9455 #define FMPI2C_CR2_HEAD10R_Pos (12U)
9456 #define FMPI2C_CR2_HEAD10R_Msk (0x1UL << FMPI2C_CR2_HEAD10R_Pos)
9457 #define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk
9458 #define FMPI2C_CR2_START_Pos (13U)
9459 #define FMPI2C_CR2_START_Msk (0x1UL << FMPI2C_CR2_START_Pos)
9460 #define FMPI2C_CR2_START FMPI2C_CR2_START_Msk
9461 #define FMPI2C_CR2_STOP_Pos (14U)
9462 #define FMPI2C_CR2_STOP_Msk (0x1UL << FMPI2C_CR2_STOP_Pos)
9463 #define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk
9464 #define FMPI2C_CR2_NACK_Pos (15U)
9465 #define FMPI2C_CR2_NACK_Msk (0x1UL << FMPI2C_CR2_NACK_Pos)
9466 #define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk
9467 #define FMPI2C_CR2_NBYTES_Pos (16U)
9468 #define FMPI2C_CR2_NBYTES_Msk (0xFFUL << FMPI2C_CR2_NBYTES_Pos)
9469 #define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk
9470 #define FMPI2C_CR2_RELOAD_Pos (24U)
9471 #define FMPI2C_CR2_RELOAD_Msk (0x1UL << FMPI2C_CR2_RELOAD_Pos)
9472 #define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk
9473 #define FMPI2C_CR2_AUTOEND_Pos (25U)
9474 #define FMPI2C_CR2_AUTOEND_Msk (0x1UL << FMPI2C_CR2_AUTOEND_Pos)
9475 #define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk
9476 #define FMPI2C_CR2_PECBYTE_Pos (26U)
9477 #define FMPI2C_CR2_PECBYTE_Msk (0x1UL << FMPI2C_CR2_PECBYTE_Pos)
9478 #define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk
9480 /******************* Bit definition for I2C_OAR1 register ******************/
9481 #define FMPI2C_OAR1_OA1_Pos (0U)
9482 #define FMPI2C_OAR1_OA1_Msk (0x3FFUL << FMPI2C_OAR1_OA1_Pos)
9483 #define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk
9484 #define FMPI2C_OAR1_OA1MODE_Pos (10U)
9485 #define FMPI2C_OAR1_OA1MODE_Msk (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)
9486 #define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk
9487 #define FMPI2C_OAR1_OA1EN_Pos (15U)
9488 #define FMPI2C_OAR1_OA1EN_Msk (0x1UL << FMPI2C_OAR1_OA1EN_Pos)
9489 #define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk
9491 /******************* Bit definition for I2C_OAR2 register ******************/
9492 #define FMPI2C_OAR2_OA2_Pos (1U)
9493 #define FMPI2C_OAR2_OA2_Msk (0x7FUL << FMPI2C_OAR2_OA2_Pos)
9494 #define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk
9495 #define FMPI2C_OAR2_OA2MSK_Pos (8U)
9496 #define FMPI2C_OAR2_OA2MSK_Msk (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)
9497 #define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk
9498 #define FMPI2C_OAR2_OA2EN_Pos (15U)
9499 #define FMPI2C_OAR2_OA2EN_Msk (0x1UL << FMPI2C_OAR2_OA2EN_Pos)
9500 #define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk
9502 /******************* Bit definition for I2C_TIMINGR register *******************/
9503 #define FMPI2C_TIMINGR_SCLL_Pos (0U)
9504 #define FMPI2C_TIMINGR_SCLL_Msk (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)
9505 #define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk
9506 #define FMPI2C_TIMINGR_SCLH_Pos (8U)
9507 #define FMPI2C_TIMINGR_SCLH_Msk (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)
9508 #define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk
9509 #define FMPI2C_TIMINGR_SDADEL_Pos (16U)
9510 #define FMPI2C_TIMINGR_SDADEL_Msk (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)
9511 #define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk
9512 #define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
9513 #define FMPI2C_TIMINGR_SCLDEL_Msk (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)
9514 #define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk
9515 #define FMPI2C_TIMINGR_PRESC_Pos (28U)
9516 #define FMPI2C_TIMINGR_PRESC_Msk (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)
9517 #define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk
9519 /******************* Bit definition for I2C_TIMEOUTR register *******************/
9520 #define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9521 #define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos)
9522 #define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk
9523 #define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
9524 #define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)
9525 #define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk
9526 #define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9527 #define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos)
9528 #define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk
9529 #define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9530 #define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)
9531 #define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk
9532 #define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
9533 #define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)
9534 #define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk
9536 /****************** Bit definition for I2C_ISR register *********************/
9537 #define FMPI2C_ISR_TXE_Pos (0U)
9538 #define FMPI2C_ISR_TXE_Msk (0x1UL << FMPI2C_ISR_TXE_Pos)
9539 #define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk
9540 #define FMPI2C_ISR_TXIS_Pos (1U)
9541 #define FMPI2C_ISR_TXIS_Msk (0x1UL << FMPI2C_ISR_TXIS_Pos)
9542 #define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk
9543 #define FMPI2C_ISR_RXNE_Pos (2U)
9544 #define FMPI2C_ISR_RXNE_Msk (0x1UL << FMPI2C_ISR_RXNE_Pos)
9545 #define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk
9546 #define FMPI2C_ISR_ADDR_Pos (3U)
9547 #define FMPI2C_ISR_ADDR_Msk (0x1UL << FMPI2C_ISR_ADDR_Pos)
9548 #define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk
9549 #define FMPI2C_ISR_NACKF_Pos (4U)
9550 #define FMPI2C_ISR_NACKF_Msk (0x1UL << FMPI2C_ISR_NACKF_Pos)
9551 #define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk
9552 #define FMPI2C_ISR_STOPF_Pos (5U)
9553 #define FMPI2C_ISR_STOPF_Msk (0x1UL << FMPI2C_ISR_STOPF_Pos)
9554 #define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk
9555 #define FMPI2C_ISR_TC_Pos (6U)
9556 #define FMPI2C_ISR_TC_Msk (0x1UL << FMPI2C_ISR_TC_Pos)
9557 #define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk
9558 #define FMPI2C_ISR_TCR_Pos (7U)
9559 #define FMPI2C_ISR_TCR_Msk (0x1UL << FMPI2C_ISR_TCR_Pos)
9560 #define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk
9561 #define FMPI2C_ISR_BERR_Pos (8U)
9562 #define FMPI2C_ISR_BERR_Msk (0x1UL << FMPI2C_ISR_BERR_Pos)
9563 #define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk
9564 #define FMPI2C_ISR_ARLO_Pos (9U)
9565 #define FMPI2C_ISR_ARLO_Msk (0x1UL << FMPI2C_ISR_ARLO_Pos)
9566 #define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk
9567 #define FMPI2C_ISR_OVR_Pos (10U)
9568 #define FMPI2C_ISR_OVR_Msk (0x1UL << FMPI2C_ISR_OVR_Pos)
9569 #define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk
9570 #define FMPI2C_ISR_PECERR_Pos (11U)
9571 #define FMPI2C_ISR_PECERR_Msk (0x1UL << FMPI2C_ISR_PECERR_Pos)
9572 #define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk
9573 #define FMPI2C_ISR_TIMEOUT_Pos (12U)
9574 #define FMPI2C_ISR_TIMEOUT_Msk (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)
9575 #define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk
9576 #define FMPI2C_ISR_ALERT_Pos (13U)
9577 #define FMPI2C_ISR_ALERT_Msk (0x1UL << FMPI2C_ISR_ALERT_Pos)
9578 #define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk
9579 #define FMPI2C_ISR_BUSY_Pos (15U)
9580 #define FMPI2C_ISR_BUSY_Msk (0x1UL << FMPI2C_ISR_BUSY_Pos)
9581 #define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk
9582 #define FMPI2C_ISR_DIR_Pos (16U)
9583 #define FMPI2C_ISR_DIR_Msk (0x1UL << FMPI2C_ISR_DIR_Pos)
9584 #define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk
9585 #define FMPI2C_ISR_ADDCODE_Pos (17U)
9586 #define FMPI2C_ISR_ADDCODE_Msk (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)
9587 #define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk
9589 /****************** Bit definition for I2C_ICR register *********************/
9590 #define FMPI2C_ICR_ADDRCF_Pos (3U)
9591 #define FMPI2C_ICR_ADDRCF_Msk (0x1UL << FMPI2C_ICR_ADDRCF_Pos)
9592 #define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk
9593 #define FMPI2C_ICR_NACKCF_Pos (4U)
9594 #define FMPI2C_ICR_NACKCF_Msk (0x1UL << FMPI2C_ICR_NACKCF_Pos)
9595 #define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk
9596 #define FMPI2C_ICR_STOPCF_Pos (5U)
9597 #define FMPI2C_ICR_STOPCF_Msk (0x1UL << FMPI2C_ICR_STOPCF_Pos)
9598 #define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk
9599 #define FMPI2C_ICR_BERRCF_Pos (8U)
9600 #define FMPI2C_ICR_BERRCF_Msk (0x1UL << FMPI2C_ICR_BERRCF_Pos)
9601 #define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk
9602 #define FMPI2C_ICR_ARLOCF_Pos (9U)
9603 #define FMPI2C_ICR_ARLOCF_Msk (0x1UL << FMPI2C_ICR_ARLOCF_Pos)
9604 #define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk
9605 #define FMPI2C_ICR_OVRCF_Pos (10U)
9606 #define FMPI2C_ICR_OVRCF_Msk (0x1UL << FMPI2C_ICR_OVRCF_Pos)
9607 #define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk
9608 #define FMPI2C_ICR_PECCF_Pos (11U)
9609 #define FMPI2C_ICR_PECCF_Msk (0x1UL << FMPI2C_ICR_PECCF_Pos)
9610 #define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk
9611 #define FMPI2C_ICR_TIMOUTCF_Pos (12U)
9612 #define FMPI2C_ICR_TIMOUTCF_Msk (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)
9613 #define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk
9614 #define FMPI2C_ICR_ALERTCF_Pos (13U)
9615 #define FMPI2C_ICR_ALERTCF_Msk (0x1UL << FMPI2C_ICR_ALERTCF_Pos)
9616 #define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk
9618 /****************** Bit definition for I2C_PECR register *********************/
9619 #define FMPI2C_PECR_PEC_Pos (0U)
9620 #define FMPI2C_PECR_PEC_Msk (0xFFUL << FMPI2C_PECR_PEC_Pos)
9621 #define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk
9623 /****************** Bit definition for I2C_RXDR register *********************/
9624 #define FMPI2C_RXDR_RXDATA_Pos (0U)
9625 #define FMPI2C_RXDR_RXDATA_Msk (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)
9626 #define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk
9628 /****************** Bit definition for I2C_TXDR register *********************/
9629 #define FMPI2C_TXDR_TXDATA_Pos (0U)
9630 #define FMPI2C_TXDR_TXDATA_Msk (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)
9631 #define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk
9635 /******************************************************************************/
9636 /* */
9637 /* Independent WATCHDOG */
9638 /* */
9639 /******************************************************************************/
9640 /******************* Bit definition for IWDG_KR register ********************/
9641 #define IWDG_KR_KEY_Pos (0U)
9642 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9643 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
9645 /******************* Bit definition for IWDG_PR register ********************/
9646 #define IWDG_PR_PR_Pos (0U)
9647 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9648 #define IWDG_PR_PR IWDG_PR_PR_Msk
9649 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9650 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9651 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9653 /******************* Bit definition for IWDG_RLR register *******************/
9654 #define IWDG_RLR_RL_Pos (0U)
9655 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9656 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
9658 /******************* Bit definition for IWDG_SR register ********************/
9659 #define IWDG_SR_PVU_Pos (0U)
9660 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9661 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
9662 #define IWDG_SR_RVU_Pos (1U)
9663 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9664 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
9668 /******************************************************************************/
9669 /* */
9670 /* Power Control */
9671 /* */
9672 /******************************************************************************/
9673 /******************** Bit definition for PWR_CR register ********************/
9674 #define PWR_CR_LPDS_Pos (0U)
9675 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
9676 #define PWR_CR_LPDS PWR_CR_LPDS_Msk
9677 #define PWR_CR_PDDS_Pos (1U)
9678 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
9679 #define PWR_CR_PDDS PWR_CR_PDDS_Msk
9680 #define PWR_CR_CWUF_Pos (2U)
9681 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
9682 #define PWR_CR_CWUF PWR_CR_CWUF_Msk
9683 #define PWR_CR_CSBF_Pos (3U)
9684 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
9685 #define PWR_CR_CSBF PWR_CR_CSBF_Msk
9686 #define PWR_CR_PVDE_Pos (4U)
9687 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
9688 #define PWR_CR_PVDE PWR_CR_PVDE_Msk
9690 #define PWR_CR_PLS_Pos (5U)
9691 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
9692 #define PWR_CR_PLS PWR_CR_PLS_Msk
9693 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9694 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9695 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9698 #define PWR_CR_PLS_LEV0 0x00000000U
9699 #define PWR_CR_PLS_LEV1 0x00000020U
9700 #define PWR_CR_PLS_LEV2 0x00000040U
9701 #define PWR_CR_PLS_LEV3 0x00000060U
9702 #define PWR_CR_PLS_LEV4 0x00000080U
9703 #define PWR_CR_PLS_LEV5 0x000000A0U
9704 #define PWR_CR_PLS_LEV6 0x000000C0U
9705 #define PWR_CR_PLS_LEV7 0x000000E0U
9706 #define PWR_CR_DBP_Pos (8U)
9707 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9708 #define PWR_CR_DBP PWR_CR_DBP_Msk
9709 #define PWR_CR_FPDS_Pos (9U)
9710 #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9711 #define PWR_CR_FPDS PWR_CR_FPDS_Msk
9712 #define PWR_CR_LPLVDS_Pos (10U)
9713 #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
9714 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
9715 #define PWR_CR_MRLVDS_Pos (11U)
9716 #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
9717 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
9718 #define PWR_CR_ADCDC1_Pos (13U)
9719 #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
9720 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
9721 #define PWR_CR_VOS_Pos (14U)
9722 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
9723 #define PWR_CR_VOS PWR_CR_VOS_Msk
9724 #define PWR_CR_VOS_0 0x00004000U
9725 #define PWR_CR_VOS_1 0x00008000U
9726 #define PWR_CR_ODEN_Pos (16U)
9727 #define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos)
9728 #define PWR_CR_ODEN PWR_CR_ODEN_Msk
9729 #define PWR_CR_ODSWEN_Pos (17U)
9730 #define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos)
9731 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk
9732 #define PWR_CR_UDEN_Pos (18U)
9733 #define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos)
9734 #define PWR_CR_UDEN PWR_CR_UDEN_Msk
9735 #define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos)
9736 #define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos)
9737 #define PWR_CR_FMSSR_Pos (20U)
9738 #define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos)
9739 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk
9740 #define PWR_CR_FISSR_Pos (21U)
9741 #define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos)
9742 #define PWR_CR_FISSR PWR_CR_FISSR_Msk
9744 /* Legacy define */
9745 #define PWR_CR_PMODE PWR_CR_VOS
9746 #define PWR_CR_LPUDS PWR_CR_LPLVDS
9747 #define PWR_CR_MRUDS PWR_CR_MRLVDS
9749 /******************* Bit definition for PWR_CSR register ********************/
9750 #define PWR_CSR_WUF_Pos (0U)
9751 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9752 #define PWR_CSR_WUF PWR_CSR_WUF_Msk
9753 #define PWR_CSR_SBF_Pos (1U)
9754 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9755 #define PWR_CSR_SBF PWR_CSR_SBF_Msk
9756 #define PWR_CSR_PVDO_Pos (2U)
9757 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9758 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9759 #define PWR_CSR_BRR_Pos (3U)
9760 #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9761 #define PWR_CSR_BRR PWR_CSR_BRR_Msk
9762 #define PWR_CSR_EWUP2_Pos (7U)
9763 #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
9764 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
9765 #define PWR_CSR_EWUP1_Pos (8U)
9766 #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
9767 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
9768 #define PWR_CSR_BRE_Pos (9U)
9769 #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9770 #define PWR_CSR_BRE PWR_CSR_BRE_Msk
9771 #define PWR_CSR_VOSRDY_Pos (14U)
9772 #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
9773 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
9774 #define PWR_CSR_ODRDY_Pos (16U)
9775 #define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos)
9776 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk
9777 #define PWR_CSR_ODSWRDY_Pos (17U)
9778 #define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos)
9779 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk
9780 #define PWR_CSR_UDRDY_Pos (18U)
9781 #define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos)
9782 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk
9783 /* Legacy define */
9784 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
9785 
9786 /* Legacy define */
9787 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9788 
9789 /******************************************************************************/
9790 /* */
9791 /* QUADSPI */
9792 /* */
9793 /******************************************************************************/
9794 /***************** Bit definition for QUADSPI_CR register *******************/
9795 #define QUADSPI_CR_EN_Pos (0U)
9796 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
9797 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
9798 #define QUADSPI_CR_ABORT_Pos (1U)
9799 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
9800 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
9801 #define QUADSPI_CR_DMAEN_Pos (2U)
9802 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
9803 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
9804 #define QUADSPI_CR_TCEN_Pos (3U)
9805 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
9806 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
9807 #define QUADSPI_CR_SSHIFT_Pos (4U)
9808 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
9809 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
9810 #define QUADSPI_CR_DFM_Pos (6U)
9811 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
9812 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
9813 #define QUADSPI_CR_FSEL_Pos (7U)
9814 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
9815 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
9816 #define QUADSPI_CR_FTHRES_Pos (8U)
9817 #define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
9818 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
9819 #define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
9820 #define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
9821 #define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
9822 #define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
9823 #define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
9824 #define QUADSPI_CR_TEIE_Pos (16U)
9825 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
9826 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
9827 #define QUADSPI_CR_TCIE_Pos (17U)
9828 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
9829 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
9830 #define QUADSPI_CR_FTIE_Pos (18U)
9831 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
9832 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
9833 #define QUADSPI_CR_SMIE_Pos (19U)
9834 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
9835 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
9836 #define QUADSPI_CR_TOIE_Pos (20U)
9837 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
9838 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
9839 #define QUADSPI_CR_APMS_Pos (22U)
9840 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
9841 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
9842 #define QUADSPI_CR_PMM_Pos (23U)
9843 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
9844 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
9845 #define QUADSPI_CR_PRESCALER_Pos (24U)
9846 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
9847 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
9848 #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
9849 #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
9850 #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
9851 #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
9852 #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
9853 #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
9854 #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
9855 #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
9857 /***************** Bit definition for QUADSPI_DCR register ******************/
9858 #define QUADSPI_DCR_CKMODE_Pos (0U)
9859 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
9860 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
9861 #define QUADSPI_DCR_CSHT_Pos (8U)
9862 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
9863 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
9864 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
9865 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
9866 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
9867 #define QUADSPI_DCR_FSIZE_Pos (16U)
9868 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
9869 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
9870 #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
9871 #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
9872 #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
9873 #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
9874 #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
9876 /****************** Bit definition for QUADSPI_SR register *******************/
9877 #define QUADSPI_SR_TEF_Pos (0U)
9878 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
9879 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
9880 #define QUADSPI_SR_TCF_Pos (1U)
9881 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
9882 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
9883 #define QUADSPI_SR_FTF_Pos (2U)
9884 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
9885 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
9886 #define QUADSPI_SR_SMF_Pos (3U)
9887 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
9888 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
9889 #define QUADSPI_SR_TOF_Pos (4U)
9890 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
9891 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
9892 #define QUADSPI_SR_BUSY_Pos (5U)
9893 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
9894 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
9895 #define QUADSPI_SR_FLEVEL_Pos (8U)
9896 #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
9897 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
9898 #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
9899 #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
9900 #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
9901 #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
9902 #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
9903 #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
9905 /****************** Bit definition for QUADSPI_FCR register ******************/
9906 #define QUADSPI_FCR_CTEF_Pos (0U)
9907 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
9908 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
9909 #define QUADSPI_FCR_CTCF_Pos (1U)
9910 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
9911 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
9912 #define QUADSPI_FCR_CSMF_Pos (3U)
9913 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
9914 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
9915 #define QUADSPI_FCR_CTOF_Pos (4U)
9916 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
9917 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
9919 /****************** Bit definition for QUADSPI_DLR register ******************/
9920 #define QUADSPI_DLR_DL_Pos (0U)
9921 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
9922 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
9924 /****************** Bit definition for QUADSPI_CCR register ******************/
9925 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9926 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
9927 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
9928 #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
9929 #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
9930 #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
9931 #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
9932 #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
9933 #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
9934 #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
9935 #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
9936 #define QUADSPI_CCR_IMODE_Pos (8U)
9937 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
9938 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
9939 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
9940 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
9941 #define QUADSPI_CCR_ADMODE_Pos (10U)
9942 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
9943 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
9944 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
9945 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
9946 #define QUADSPI_CCR_ADSIZE_Pos (12U)
9947 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
9948 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
9949 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
9950 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
9951 #define QUADSPI_CCR_ABMODE_Pos (14U)
9952 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
9953 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
9954 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
9955 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
9956 #define QUADSPI_CCR_ABSIZE_Pos (16U)
9957 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
9958 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
9959 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
9960 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
9961 #define QUADSPI_CCR_DCYC_Pos (18U)
9962 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
9963 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
9964 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
9965 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
9966 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
9967 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
9968 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
9969 #define QUADSPI_CCR_DMODE_Pos (24U)
9970 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
9971 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
9972 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
9973 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
9974 #define QUADSPI_CCR_FMODE_Pos (26U)
9975 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
9976 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
9977 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
9978 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
9979 #define QUADSPI_CCR_SIOO_Pos (28U)
9980 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
9981 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
9982 #define QUADSPI_CCR_DHHC_Pos (30U)
9983 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
9984 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
9985 #define QUADSPI_CCR_DDRM_Pos (31U)
9986 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
9987 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
9988 /****************** Bit definition for QUADSPI_AR register *******************/
9989 #define QUADSPI_AR_ADDRESS_Pos (0U)
9990 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
9991 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
9993 /****************** Bit definition for QUADSPI_ABR register ******************/
9994 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
9995 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
9996 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
9998 /****************** Bit definition for QUADSPI_DR register *******************/
9999 #define QUADSPI_DR_DATA_Pos (0U)
10000 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
10001 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
10003 /****************** Bit definition for QUADSPI_PSMKR register ****************/
10004 #define QUADSPI_PSMKR_MASK_Pos (0U)
10005 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
10006 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
10008 /****************** Bit definition for QUADSPI_PSMAR register ****************/
10009 #define QUADSPI_PSMAR_MATCH_Pos (0U)
10010 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
10011 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
10013 /****************** Bit definition for QUADSPI_PIR register *****************/
10014 #define QUADSPI_PIR_INTERVAL_Pos (0U)
10015 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
10016 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
10018 /****************** Bit definition for QUADSPI_LPTR register *****************/
10019 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
10020 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
10021 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
10023 /******************************************************************************/
10024 /* */
10025 /* Reset and Clock Control */
10026 /* */
10027 /******************************************************************************/
10028 /******************** Bit definition for RCC_CR register ********************/
10029 #define RCC_CR_HSION_Pos (0U)
10030 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10031 #define RCC_CR_HSION RCC_CR_HSION_Msk
10032 #define RCC_CR_HSIRDY_Pos (1U)
10033 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10034 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10035 
10036 #define RCC_CR_HSITRIM_Pos (3U)
10037 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
10038 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10039 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
10040 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
10041 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
10042 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
10043 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
10045 #define RCC_CR_HSICAL_Pos (8U)
10046 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
10047 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10048 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
10049 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
10050 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
10051 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
10052 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
10053 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
10054 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
10055 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
10057 #define RCC_CR_HSEON_Pos (16U)
10058 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10059 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
10060 #define RCC_CR_HSERDY_Pos (17U)
10061 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10062 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10063 #define RCC_CR_HSEBYP_Pos (18U)
10064 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10065 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10066 #define RCC_CR_CSSON_Pos (19U)
10067 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10068 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
10069 #define RCC_CR_PLLON_Pos (24U)
10070 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10071 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
10072 #define RCC_CR_PLLRDY_Pos (25U)
10073 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10074 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10075 /*
10076  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10077  */
10078 #define RCC_PLLI2S_SUPPORT
10080 #define RCC_CR_PLLI2SON_Pos (26U)
10081 #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
10082 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10083 #define RCC_CR_PLLI2SRDY_Pos (27U)
10084 #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
10085 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10086 /*
10087  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10088  */
10089 #define RCC_PLLSAI_SUPPORT
10091 #define RCC_CR_PLLSAION_Pos (28U)
10092 #define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
10093 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10094 #define RCC_CR_PLLSAIRDY_Pos (29U)
10095 #define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
10096 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10097 
10098 /******************** Bit definition for RCC_PLLCFGR register ***************/
10099 #define RCC_PLLCFGR_PLLM_Pos (0U)
10100 #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
10101 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10102 #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
10103 #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
10104 #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
10105 #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
10106 #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
10107 #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
10109 #define RCC_PLLCFGR_PLLN_Pos (6U)
10110 #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
10111 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10112 #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
10113 #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
10114 #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
10115 #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
10116 #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
10117 #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
10118 #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
10119 #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
10120 #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
10122 #define RCC_PLLCFGR_PLLP_Pos (16U)
10123 #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
10124 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10125 #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
10126 #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
10128 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
10129 #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
10130 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10131 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10132 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
10133 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10134 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10135 
10136 #define RCC_PLLCFGR_PLLQ_Pos (24U)
10137 #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
10138 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10139 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
10140 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
10141 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
10142 #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
10143 /*
10144  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10145  */
10146 #define RCC_PLLR_SYSCLK_SUPPORT
10147 #define RCC_PLLR_I2S_CLKSOURCE_SUPPORT
10149 #define RCC_PLLCFGR_PLLR_Pos (28U)
10150 #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
10151 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10152 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
10153 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
10154 #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
10156 /******************** Bit definition for RCC_CFGR register ******************/
10158 #define RCC_CFGR_SW_Pos (0U)
10159 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10160 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
10161 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10162 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10164 #define RCC_CFGR_SW_HSI 0x00000000U
10165 #define RCC_CFGR_SW_HSE 0x00000001U
10166 #define RCC_CFGR_SW_PLL 0x00000002U
10167 #define RCC_CFGR_SW_PLLR 0x00000003U
10170 #define RCC_CFGR_SWS_Pos (2U)
10171 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10172 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10173 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10174 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10176 #define RCC_CFGR_SWS_HSI 0x00000000U
10177 #define RCC_CFGR_SWS_HSE 0x00000004U
10178 #define RCC_CFGR_SWS_PLL 0x00000008U
10179 #define RCC_CFGR_SWS_PLLR 0x0000000CU
10182 #define RCC_CFGR_HPRE_Pos (4U)
10183 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10184 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10185 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10186 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10187 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10188 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10190 #define RCC_CFGR_HPRE_DIV1 0x00000000U
10191 #define RCC_CFGR_HPRE_DIV2 0x00000080U
10192 #define RCC_CFGR_HPRE_DIV4 0x00000090U
10193 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
10194 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
10195 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
10196 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
10197 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
10198 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
10201 #define RCC_CFGR_PPRE1_Pos (10U)
10202 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10203 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10204 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10205 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10206 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10208 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
10209 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
10210 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
10211 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
10212 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
10215 #define RCC_CFGR_PPRE2_Pos (13U)
10216 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10217 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10218 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10219 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10220 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10222 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
10223 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
10224 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
10225 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
10226 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
10229 #define RCC_CFGR_RTCPRE_Pos (16U)
10230 #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
10231 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10232 #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
10233 #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
10234 #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
10235 #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
10236 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
10239 #define RCC_CFGR_MCO1_Pos (21U)
10240 #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
10241 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10242 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
10243 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
10246 #define RCC_CFGR_MCO1PRE_Pos (24U)
10247 #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
10248 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10249 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
10250 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
10251 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
10253 #define RCC_CFGR_MCO2PRE_Pos (27U)
10254 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
10255 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10256 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
10257 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
10258 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
10260 #define RCC_CFGR_MCO2_Pos (30U)
10261 #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
10262 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10263 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
10264 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
10266 /******************** Bit definition for RCC_CIR register *******************/
10267 #define RCC_CIR_LSIRDYF_Pos (0U)
10268 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
10269 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10270 #define RCC_CIR_LSERDYF_Pos (1U)
10271 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
10272 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10273 #define RCC_CIR_HSIRDYF_Pos (2U)
10274 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
10275 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10276 #define RCC_CIR_HSERDYF_Pos (3U)
10277 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
10278 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10279 #define RCC_CIR_PLLRDYF_Pos (4U)
10280 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
10281 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10282 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
10283 #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
10284 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10285 
10286 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
10287 #define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
10288 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10289 #define RCC_CIR_CSSF_Pos (7U)
10290 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
10291 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10292 #define RCC_CIR_LSIRDYIE_Pos (8U)
10293 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
10294 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10295 #define RCC_CIR_LSERDYIE_Pos (9U)
10296 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
10297 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10298 #define RCC_CIR_HSIRDYIE_Pos (10U)
10299 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
10300 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10301 #define RCC_CIR_HSERDYIE_Pos (11U)
10302 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
10303 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10304 #define RCC_CIR_PLLRDYIE_Pos (12U)
10305 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
10306 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10307 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10308 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
10309 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10310 
10311 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10312 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
10313 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10314 #define RCC_CIR_LSIRDYC_Pos (16U)
10315 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
10316 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10317 #define RCC_CIR_LSERDYC_Pos (17U)
10318 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
10319 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10320 #define RCC_CIR_HSIRDYC_Pos (18U)
10321 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
10322 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10323 #define RCC_CIR_HSERDYC_Pos (19U)
10324 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
10325 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10326 #define RCC_CIR_PLLRDYC_Pos (20U)
10327 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
10328 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10329 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
10330 #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
10331 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10332 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
10333 #define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
10334 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10335 
10336 #define RCC_CIR_CSSC_Pos (23U)
10337 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
10338 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10339 
10340 /******************** Bit definition for RCC_AHB1RSTR register **************/
10341 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10342 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
10343 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10344 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10345 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
10346 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10347 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10348 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
10349 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10350 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10351 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
10352 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10353 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10354 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
10355 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10356 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10357 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
10358 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10359 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10360 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
10361 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10362 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10363 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
10364 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10365 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
10366 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
10367 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10368 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10369 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
10370 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10371 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10372 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
10373 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10374 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10375 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
10376 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10377 
10378 /******************** Bit definition for RCC_AHB2RSTR register **************/
10379 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10380 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
10381 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10382 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10383 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
10384 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10385 /******************** Bit definition for RCC_AHB3RSTR register **************/
10386 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
10387 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
10388 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10389 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
10390 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
10391 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
10392 
10393 
10394 /******************** Bit definition for RCC_APB1RSTR register **************/
10395 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
10396 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
10397 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10398 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
10399 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
10400 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10401 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
10402 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
10403 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10404 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
10405 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
10406 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10407 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
10408 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
10409 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10410 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
10411 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
10412 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10413 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
10414 #define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
10415 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10416 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
10417 #define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
10418 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10419 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
10420 #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
10421 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10422 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
10423 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
10424 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10425 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
10426 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
10427 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10428 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
10429 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
10430 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10431 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
10432 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos)
10433 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
10434 #define RCC_APB1RSTR_USART2RST_Pos (17U)
10435 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
10436 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10437 #define RCC_APB1RSTR_USART3RST_Pos (18U)
10438 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
10439 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10440 #define RCC_APB1RSTR_UART4RST_Pos (19U)
10441 #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
10442 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10443 #define RCC_APB1RSTR_UART5RST_Pos (20U)
10444 #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
10445 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10446 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
10447 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
10448 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10449 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
10450 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
10451 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10452 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
10453 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
10454 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10455 #define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
10456 #define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos)
10457 #define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
10458 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
10459 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
10460 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10461 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
10462 #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
10463 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10464 #define RCC_APB1RSTR_CECRST_Pos (27U)
10465 #define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos)
10466 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
10467 #define RCC_APB1RSTR_PWRRST_Pos (28U)
10468 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
10469 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10470 #define RCC_APB1RSTR_DACRST_Pos (29U)
10471 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
10472 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10473 
10474 /******************** Bit definition for RCC_APB2RSTR register **************/
10475 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
10476 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
10477 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10478 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
10479 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
10480 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10481 #define RCC_APB2RSTR_USART1RST_Pos (4U)
10482 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
10483 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10484 #define RCC_APB2RSTR_USART6RST_Pos (5U)
10485 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
10486 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10487 #define RCC_APB2RSTR_ADCRST_Pos (8U)
10488 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
10489 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10490 #define RCC_APB2RSTR_SDIORST_Pos (11U)
10491 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
10492 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
10493 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
10494 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
10495 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10496 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
10497 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
10498 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10499 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10500 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
10501 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10502 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
10503 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
10504 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10505 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
10506 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
10507 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10508 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
10509 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
10510 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10511 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
10512 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
10513 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10514 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
10515 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
10516 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
10517 
10518 /* Old SPI1RST bit definition, maintained for legacy purpose */
10519 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
10520 
10521 /******************** Bit definition for RCC_AHB1ENR register ***************/
10522 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
10523 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
10524 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
10525 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
10526 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
10527 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
10528 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
10529 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
10530 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
10531 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
10532 #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
10533 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
10534 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
10535 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
10536 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
10537 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
10538 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
10539 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
10540 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
10541 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
10542 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
10543 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
10544 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
10545 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
10546 #define RCC_AHB1ENR_CRCEN_Pos (12U)
10547 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
10548 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10549 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
10550 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
10551 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
10552 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
10553 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
10554 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10555 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
10556 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
10557 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10558 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
10559 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
10560 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
10561 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
10562 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
10563 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
10564 /******************** Bit definition for RCC_AHB2ENR register ***************/
10565 /*
10566  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10567  */
10568 #define RCC_AHB2_SUPPORT
10570 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
10571 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
10572 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
10573 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
10574 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
10575 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
10576 
10577 /******************** Bit definition for RCC_AHB3ENR register ***************/
10578 /*
10579  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10580  */
10581 #define RCC_AHB3_SUPPORT
10583 #define RCC_AHB3ENR_FMCEN_Pos (0U)
10584 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
10585 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
10586 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
10587 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
10588 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
10589 
10590 /******************** Bit definition for RCC_APB1ENR register ***************/
10591 #define RCC_APB1ENR_TIM2EN_Pos (0U)
10592 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
10593 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
10594 #define RCC_APB1ENR_TIM3EN_Pos (1U)
10595 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
10596 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
10597 #define RCC_APB1ENR_TIM4EN_Pos (2U)
10598 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
10599 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
10600 #define RCC_APB1ENR_TIM5EN_Pos (3U)
10601 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
10602 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
10603 #define RCC_APB1ENR_TIM6EN_Pos (4U)
10604 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
10605 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
10606 #define RCC_APB1ENR_TIM7EN_Pos (5U)
10607 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
10608 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
10609 #define RCC_APB1ENR_TIM12EN_Pos (6U)
10610 #define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
10611 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
10612 #define RCC_APB1ENR_TIM13EN_Pos (7U)
10613 #define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
10614 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
10615 #define RCC_APB1ENR_TIM14EN_Pos (8U)
10616 #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
10617 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10618 #define RCC_APB1ENR_WWDGEN_Pos (11U)
10619 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
10620 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10621 #define RCC_APB1ENR_SPI2EN_Pos (14U)
10622 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
10623 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10624 #define RCC_APB1ENR_SPI3EN_Pos (15U)
10625 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
10626 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10627 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
10628 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos)
10629 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
10630 #define RCC_APB1ENR_USART2EN_Pos (17U)
10631 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
10632 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10633 #define RCC_APB1ENR_USART3EN_Pos (18U)
10634 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
10635 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10636 #define RCC_APB1ENR_UART4EN_Pos (19U)
10637 #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
10638 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10639 #define RCC_APB1ENR_UART5EN_Pos (20U)
10640 #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
10641 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10642 #define RCC_APB1ENR_I2C1EN_Pos (21U)
10643 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
10644 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10645 #define RCC_APB1ENR_I2C2EN_Pos (22U)
10646 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
10647 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10648 #define RCC_APB1ENR_I2C3EN_Pos (23U)
10649 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
10650 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10651 #define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
10652 #define RCC_APB1ENR_FMPI2C1EN_Msk (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos)
10653 #define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
10654 #define RCC_APB1ENR_CAN1EN_Pos (25U)
10655 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
10656 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10657 #define RCC_APB1ENR_CAN2EN_Pos (26U)
10658 #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
10659 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10660 #define RCC_APB1ENR_CECEN_Pos (27U)
10661 #define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos)
10662 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
10663 #define RCC_APB1ENR_PWREN_Pos (28U)
10664 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
10665 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10666 #define RCC_APB1ENR_DACEN_Pos (29U)
10667 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
10668 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10669 
10670 /******************** Bit definition for RCC_APB2ENR register ***************/
10671 #define RCC_APB2ENR_TIM1EN_Pos (0U)
10672 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
10673 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10674 #define RCC_APB2ENR_TIM8EN_Pos (1U)
10675 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
10676 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10677 #define RCC_APB2ENR_USART1EN_Pos (4U)
10678 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
10679 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10680 #define RCC_APB2ENR_USART6EN_Pos (5U)
10681 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
10682 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10683 #define RCC_APB2ENR_ADC1EN_Pos (8U)
10684 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
10685 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10686 #define RCC_APB2ENR_ADC2EN_Pos (9U)
10687 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
10688 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10689 #define RCC_APB2ENR_ADC3EN_Pos (10U)
10690 #define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
10691 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10692 #define RCC_APB2ENR_SDIOEN_Pos (11U)
10693 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
10694 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10695 #define RCC_APB2ENR_SPI1EN_Pos (12U)
10696 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
10697 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10698 #define RCC_APB2ENR_SPI4EN_Pos (13U)
10699 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
10700 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
10701 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10702 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
10703 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10704 #define RCC_APB2ENR_TIM9EN_Pos (16U)
10705 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
10706 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10707 #define RCC_APB2ENR_TIM10EN_Pos (17U)
10708 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
10709 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10710 #define RCC_APB2ENR_TIM11EN_Pos (18U)
10711 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
10712 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10713 #define RCC_APB2ENR_SAI1EN_Pos (22U)
10714 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
10715 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
10716 #define RCC_APB2ENR_SAI2EN_Pos (23U)
10717 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
10718 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
10719 
10720 /******************** Bit definition for RCC_AHB1LPENR register *************/
10721 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10722 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
10723 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10724 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10725 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
10726 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10727 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10728 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
10729 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10730 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10731 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
10732 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10733 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10734 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
10735 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10736 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10737 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
10738 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10739 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10740 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
10741 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10742 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10743 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
10744 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10745 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10746 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
10747 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10748 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10749 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
10750 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10751 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10752 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
10753 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10754 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10755 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
10756 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10757 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10758 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
10759 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10760 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10761 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
10762 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10763 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10764 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
10765 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10766 
10767 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10768 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
10769 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10770 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10771 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
10772 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10773 
10774 /******************** Bit definition for RCC_AHB2LPENR register *************/
10775 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
10776 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
10777 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
10778 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10779 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
10780 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10781 
10782 /******************** Bit definition for RCC_AHB3LPENR register *************/
10783 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
10784 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
10785 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
10786 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
10787 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
10788 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
10789 
10790 /******************** Bit definition for RCC_APB1LPENR register *************/
10791 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10792 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
10793 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10794 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10795 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
10796 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10797 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10798 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
10799 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10800 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10801 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
10802 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10803 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10804 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
10805 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10806 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10807 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
10808 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10809 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10810 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
10811 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10812 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10813 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
10814 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10815 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10816 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
10817 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10818 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10819 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
10820 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10821 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10822 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
10823 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10824 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10825 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
10826 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10827 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
10828 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos)
10829 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
10830 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10831 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
10832 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10833 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10834 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
10835 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10836 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10837 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
10838 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10839 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10840 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
10841 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10842 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10843 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
10844 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10845 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10846 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
10847 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10848 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10849 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
10850 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10851 #define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
10852 #define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos)
10853 #define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
10854 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10855 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
10856 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10857 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10858 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
10859 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10860 #define RCC_APB1LPENR_CECLPEN_Pos (27U)
10861 #define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos)
10862 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
10863 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10864 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
10865 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10866 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
10867 #define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
10868 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10869 
10870 /******************** Bit definition for RCC_APB2LPENR register *************/
10871 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10872 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
10873 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10874 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10875 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
10876 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10877 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10878 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
10879 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10880 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10881 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
10882 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10883 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10884 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
10885 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10886 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10887 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
10888 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10889 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10890 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
10891 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10892 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10893 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
10894 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10895 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10896 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
10897 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10898 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
10899 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
10900 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
10901 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10902 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
10903 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10904 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10905 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
10906 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10907 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10908 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
10909 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10910 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10911 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
10912 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10913 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
10914 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
10915 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
10916 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
10917 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
10918 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
10919 
10920 /******************** Bit definition for RCC_BDCR register ******************/
10921 #define RCC_BDCR_LSEON_Pos (0U)
10922 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10923 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10924 #define RCC_BDCR_LSERDY_Pos (1U)
10925 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10926 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10927 #define RCC_BDCR_LSEBYP_Pos (2U)
10928 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10929 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10930 #define RCC_BDCR_LSEMOD_Pos (3U)
10931 #define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
10932 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
10933 
10934 #define RCC_BDCR_RTCSEL_Pos (8U)
10935 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10936 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10937 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10938 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10940 #define RCC_BDCR_RTCEN_Pos (15U)
10941 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10942 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10943 #define RCC_BDCR_BDRST_Pos (16U)
10944 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10945 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10946 
10947 /******************** Bit definition for RCC_CSR register *******************/
10948 #define RCC_CSR_LSION_Pos (0U)
10949 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10950 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
10951 #define RCC_CSR_LSIRDY_Pos (1U)
10952 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10953 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10954 #define RCC_CSR_RMVF_Pos (24U)
10955 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10956 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10957 #define RCC_CSR_BORRSTF_Pos (25U)
10958 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10959 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10960 #define RCC_CSR_PINRSTF_Pos (26U)
10961 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10962 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10963 #define RCC_CSR_PORRSTF_Pos (27U)
10964 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10965 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10966 #define RCC_CSR_SFTRSTF_Pos (28U)
10967 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10968 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10969 #define RCC_CSR_IWDGRSTF_Pos (29U)
10970 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10971 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10972 #define RCC_CSR_WWDGRSTF_Pos (30U)
10973 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10974 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10975 #define RCC_CSR_LPWRRSTF_Pos (31U)
10976 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10977 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10978 /* Legacy defines */
10979 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10980 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10981 
10982 /******************** Bit definition for RCC_SSCGR register *****************/
10983 #define RCC_SSCGR_MODPER_Pos (0U)
10984 #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10985 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10986 #define RCC_SSCGR_INCSTEP_Pos (13U)
10987 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10988 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10989 #define RCC_SSCGR_SPREADSEL_Pos (30U)
10990 #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10991 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10992 #define RCC_SSCGR_SSCGEN_Pos (31U)
10993 #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10994 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10995 
10996 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
10997 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
10998 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10999 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
11000 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
11001 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
11002 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
11003 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
11004 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
11005 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
11007 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11008 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11009 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11010 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11011 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11012 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11013 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11014 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11015 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11016 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11017 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11018 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11020 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
11021 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
11022 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
11023 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
11024 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
11025 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11026 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11027 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11028 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11029 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11030 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11031 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11032 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11033 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11034 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11035 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11036 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11037 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11039 /******************** Bit definition for RCC_PLLSAICFGR register ************/
11040 #define RCC_PLLSAICFGR_PLLSAIM_Pos (0U)
11041 #define RCC_PLLSAICFGR_PLLSAIM_Msk (0x3FUL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11042 #define RCC_PLLSAICFGR_PLLSAIM RCC_PLLSAICFGR_PLLSAIM_Msk
11043 #define RCC_PLLSAICFGR_PLLSAIM_0 (0x01UL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11044 #define RCC_PLLSAICFGR_PLLSAIM_1 (0x02UL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11045 #define RCC_PLLSAICFGR_PLLSAIM_2 (0x04UL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11046 #define RCC_PLLSAICFGR_PLLSAIM_3 (0x08UL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11047 #define RCC_PLLSAICFGR_PLLSAIM_4 (0x10UL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11048 #define RCC_PLLSAICFGR_PLLSAIM_5 (0x20UL << RCC_PLLSAICFGR_PLLSAIM_Pos)
11049 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11050 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11051 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11052 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11053 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11054 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11055 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11056 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11057 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11058 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11059 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11060 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11062 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
11063 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
11064 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
11065 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
11066 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
11068 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11069 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11070 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11071 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11072 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11073 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11074 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11077 /******************** Bit definition for RCC_DCKCFGR register ***************/
11078 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
11079 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11080 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
11081 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11082 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11083 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11084 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11085 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
11087 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
11088 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11089 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
11090 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11091 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11092 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11093 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11094 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
11095 #define RCC_DCKCFGR_SAI1SRC_Pos (20U)
11096 #define RCC_DCKCFGR_SAI1SRC_Msk (0x3UL << RCC_DCKCFGR_SAI1SRC_Pos)
11097 #define RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_Msk
11098 #define RCC_DCKCFGR_SAI1SRC_0 (0x1UL << RCC_DCKCFGR_SAI1SRC_Pos)
11099 #define RCC_DCKCFGR_SAI1SRC_1 (0x2UL << RCC_DCKCFGR_SAI1SRC_Pos)
11100 #define RCC_DCKCFGR_SAI2SRC_Pos (22U)
11101 #define RCC_DCKCFGR_SAI2SRC_Msk (0x3UL << RCC_DCKCFGR_SAI2SRC_Pos)
11102 #define RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_Msk
11103 #define RCC_DCKCFGR_SAI2SRC_0 (0x1UL << RCC_DCKCFGR_SAI2SRC_Pos)
11104 #define RCC_DCKCFGR_SAI2SRC_1 (0x2UL << RCC_DCKCFGR_SAI2SRC_Pos)
11106 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
11107 #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
11108 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
11109 #define RCC_DCKCFGR_I2S1SRC_Pos (25U)
11110 #define RCC_DCKCFGR_I2S1SRC_Msk (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)
11111 #define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
11112 #define RCC_DCKCFGR_I2S1SRC_0 (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)
11113 #define RCC_DCKCFGR_I2S1SRC_1 (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)
11115 #define RCC_DCKCFGR_I2S2SRC_Pos (27U)
11116 #define RCC_DCKCFGR_I2S2SRC_Msk (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)
11117 #define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
11118 #define RCC_DCKCFGR_I2S2SRC_0 (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)
11119 #define RCC_DCKCFGR_I2S2SRC_1 (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)
11121 /******************** Bit definition for RCC_CKGATENR register ***************/
11122 #define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
11123 #define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos)
11124 #define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
11125 #define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
11126 #define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos)
11127 #define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
11128 #define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
11129 #define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos)
11130 #define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
11131 #define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
11132 #define RCC_CKGATENR_SPARE_CKEN_Msk (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos)
11133 #define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
11134 #define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
11135 #define RCC_CKGATENR_SRAM_CKEN_Msk (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos)
11136 #define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
11137 #define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
11138 #define RCC_CKGATENR_FLITF_CKEN_Msk (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos)
11139 #define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
11140 #define RCC_CKGATENR_RCC_CKEN_Pos (6U)
11141 #define RCC_CKGATENR_RCC_CKEN_Msk (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos)
11142 #define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
11143 
11144 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
11145 #define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
11146 #define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
11147 #define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
11148 #define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
11149 #define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
11150 #define RCC_DCKCFGR2_CECSEL_Pos (26U)
11151 #define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)
11152 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
11153 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
11154 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
11155 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
11156 #define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
11157 #define RCC_DCKCFGR2_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)
11158 #define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
11159 #define RCC_DCKCFGR2_SPDIFRXSEL_Pos (29U)
11160 #define RCC_DCKCFGR2_SPDIFRXSEL_Msk (0x1UL << RCC_DCKCFGR2_SPDIFRXSEL_Pos)
11161 #define RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_Msk
11162 
11163 
11164 /******************************************************************************/
11165 /* */
11166 /* Real-Time Clock (RTC) */
11167 /* */
11168 /******************************************************************************/
11169 /*
11170  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11171  */
11172 #define RTC_TAMPER2_SUPPORT
11173 #define RTC_AF2_SUPPORT
11174 /******************** Bits definition for RTC_TR register *******************/
11175 #define RTC_TR_PM_Pos (22U)
11176 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11177 #define RTC_TR_PM RTC_TR_PM_Msk
11178 #define RTC_TR_HT_Pos (20U)
11179 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11180 #define RTC_TR_HT RTC_TR_HT_Msk
11181 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11182 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11183 #define RTC_TR_HU_Pos (16U)
11184 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11185 #define RTC_TR_HU RTC_TR_HU_Msk
11186 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11187 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11188 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11189 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11190 #define RTC_TR_MNT_Pos (12U)
11191 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11192 #define RTC_TR_MNT RTC_TR_MNT_Msk
11193 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11194 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11195 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11196 #define RTC_TR_MNU_Pos (8U)
11197 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11198 #define RTC_TR_MNU RTC_TR_MNU_Msk
11199 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11200 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11201 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11202 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11203 #define RTC_TR_ST_Pos (4U)
11204 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11205 #define RTC_TR_ST RTC_TR_ST_Msk
11206 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11207 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11208 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11209 #define RTC_TR_SU_Pos (0U)
11210 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11211 #define RTC_TR_SU RTC_TR_SU_Msk
11212 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11213 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11214 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11215 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11217 /******************** Bits definition for RTC_DR register *******************/
11218 #define RTC_DR_YT_Pos (20U)
11219 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11220 #define RTC_DR_YT RTC_DR_YT_Msk
11221 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11222 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11223 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11224 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11225 #define RTC_DR_YU_Pos (16U)
11226 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11227 #define RTC_DR_YU RTC_DR_YU_Msk
11228 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11229 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11230 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11231 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11232 #define RTC_DR_WDU_Pos (13U)
11233 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11234 #define RTC_DR_WDU RTC_DR_WDU_Msk
11235 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11236 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11237 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11238 #define RTC_DR_MT_Pos (12U)
11239 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11240 #define RTC_DR_MT RTC_DR_MT_Msk
11241 #define RTC_DR_MU_Pos (8U)
11242 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11243 #define RTC_DR_MU RTC_DR_MU_Msk
11244 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11245 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11246 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11247 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11248 #define RTC_DR_DT_Pos (4U)
11249 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11250 #define RTC_DR_DT RTC_DR_DT_Msk
11251 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11252 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11253 #define RTC_DR_DU_Pos (0U)
11254 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11255 #define RTC_DR_DU RTC_DR_DU_Msk
11256 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11257 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11258 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11259 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11261 /******************** Bits definition for RTC_CR register *******************/
11262 #define RTC_CR_COE_Pos (23U)
11263 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11264 #define RTC_CR_COE RTC_CR_COE_Msk
11265 #define RTC_CR_OSEL_Pos (21U)
11266 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11267 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
11268 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11269 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11270 #define RTC_CR_POL_Pos (20U)
11271 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11272 #define RTC_CR_POL RTC_CR_POL_Msk
11273 #define RTC_CR_COSEL_Pos (19U)
11274 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11275 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
11276 #define RTC_CR_BKP_Pos (18U)
11277 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11278 #define RTC_CR_BKP RTC_CR_BKP_Msk
11279 #define RTC_CR_SUB1H_Pos (17U)
11280 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11281 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11282 #define RTC_CR_ADD1H_Pos (16U)
11283 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11284 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11285 #define RTC_CR_TSIE_Pos (15U)
11286 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11287 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
11288 #define RTC_CR_WUTIE_Pos (14U)
11289 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11290 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11291 #define RTC_CR_ALRBIE_Pos (13U)
11292 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11293 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11294 #define RTC_CR_ALRAIE_Pos (12U)
11295 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11296 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11297 #define RTC_CR_TSE_Pos (11U)
11298 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11299 #define RTC_CR_TSE RTC_CR_TSE_Msk
11300 #define RTC_CR_WUTE_Pos (10U)
11301 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11302 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
11303 #define RTC_CR_ALRBE_Pos (9U)
11304 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11305 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11306 #define RTC_CR_ALRAE_Pos (8U)
11307 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11308 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11309 #define RTC_CR_DCE_Pos (7U)
11310 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
11311 #define RTC_CR_DCE RTC_CR_DCE_Msk
11312 #define RTC_CR_FMT_Pos (6U)
11313 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11314 #define RTC_CR_FMT RTC_CR_FMT_Msk
11315 #define RTC_CR_BYPSHAD_Pos (5U)
11316 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11317 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11318 #define RTC_CR_REFCKON_Pos (4U)
11319 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11320 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11321 #define RTC_CR_TSEDGE_Pos (3U)
11322 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11323 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11324 #define RTC_CR_WUCKSEL_Pos (0U)
11325 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11326 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11327 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11328 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11329 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11331 /* Legacy defines */
11332 #define RTC_CR_BCK RTC_CR_BKP
11333 
11334 /******************** Bits definition for RTC_ISR register ******************/
11335 #define RTC_ISR_RECALPF_Pos (16U)
11336 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11337 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11338 #define RTC_ISR_TAMP1F_Pos (13U)
11339 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11340 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11341 #define RTC_ISR_TAMP2F_Pos (14U)
11342 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11343 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11344 #define RTC_ISR_TSOVF_Pos (12U)
11345 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11346 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11347 #define RTC_ISR_TSF_Pos (11U)
11348 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11349 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
11350 #define RTC_ISR_WUTF_Pos (10U)
11351 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11352 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11353 #define RTC_ISR_ALRBF_Pos (9U)
11354 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11355 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11356 #define RTC_ISR_ALRAF_Pos (8U)
11357 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11358 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11359 #define RTC_ISR_INIT_Pos (7U)
11360 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11361 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
11362 #define RTC_ISR_INITF_Pos (6U)
11363 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11364 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
11365 #define RTC_ISR_RSF_Pos (5U)
11366 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11367 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
11368 #define RTC_ISR_INITS_Pos (4U)
11369 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11370 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
11371 #define RTC_ISR_SHPF_Pos (3U)
11372 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11373 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11374 #define RTC_ISR_WUTWF_Pos (2U)
11375 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11376 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11377 #define RTC_ISR_ALRBWF_Pos (1U)
11378 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
11379 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11380 #define RTC_ISR_ALRAWF_Pos (0U)
11381 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
11382 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11383 
11384 /******************** Bits definition for RTC_PRER register *****************/
11385 #define RTC_PRER_PREDIV_A_Pos (16U)
11386 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
11387 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11388 #define RTC_PRER_PREDIV_S_Pos (0U)
11389 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
11390 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11391 
11392 /******************** Bits definition for RTC_WUTR register *****************/
11393 #define RTC_WUTR_WUT_Pos (0U)
11394 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
11395 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11396 
11397 /******************** Bits definition for RTC_CALIBR register ***************/
11398 #define RTC_CALIBR_DCS_Pos (7U)
11399 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
11400 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
11401 #define RTC_CALIBR_DC_Pos (0U)
11402 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
11403 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
11404 
11405 /******************** Bits definition for RTC_ALRMAR register ***************/
11406 #define RTC_ALRMAR_MSK4_Pos (31U)
11407 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11408 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11409 #define RTC_ALRMAR_WDSEL_Pos (30U)
11410 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11411 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11412 #define RTC_ALRMAR_DT_Pos (28U)
11413 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11414 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11415 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11416 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11417 #define RTC_ALRMAR_DU_Pos (24U)
11418 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11419 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11420 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11421 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11422 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11423 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11424 #define RTC_ALRMAR_MSK3_Pos (23U)
11425 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11426 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11427 #define RTC_ALRMAR_PM_Pos (22U)
11428 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11429 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11430 #define RTC_ALRMAR_HT_Pos (20U)
11431 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11432 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11433 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11434 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11435 #define RTC_ALRMAR_HU_Pos (16U)
11436 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11437 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11438 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11439 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11440 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11441 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11442 #define RTC_ALRMAR_MSK2_Pos (15U)
11443 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
11444 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11445 #define RTC_ALRMAR_MNT_Pos (12U)
11446 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
11447 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11448 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
11449 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
11450 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
11451 #define RTC_ALRMAR_MNU_Pos (8U)
11452 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
11453 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11454 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
11455 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
11456 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
11457 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
11458 #define RTC_ALRMAR_MSK1_Pos (7U)
11459 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
11460 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11461 #define RTC_ALRMAR_ST_Pos (4U)
11462 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
11463 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11464 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
11465 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
11466 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
11467 #define RTC_ALRMAR_SU_Pos (0U)
11468 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
11469 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11470 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
11471 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
11472 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
11473 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
11475 /******************** Bits definition for RTC_ALRMBR register ***************/
11476 #define RTC_ALRMBR_MSK4_Pos (31U)
11477 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
11478 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11479 #define RTC_ALRMBR_WDSEL_Pos (30U)
11480 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
11481 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11482 #define RTC_ALRMBR_DT_Pos (28U)
11483 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
11484 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11485 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
11486 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
11487 #define RTC_ALRMBR_DU_Pos (24U)
11488 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
11489 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11490 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
11491 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
11492 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
11493 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
11494 #define RTC_ALRMBR_MSK3_Pos (23U)
11495 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
11496 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11497 #define RTC_ALRMBR_PM_Pos (22U)
11498 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
11499 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11500 #define RTC_ALRMBR_HT_Pos (20U)
11501 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
11502 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11503 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
11504 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
11505 #define RTC_ALRMBR_HU_Pos (16U)
11506 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
11507 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11508 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
11509 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
11510 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
11511 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
11512 #define RTC_ALRMBR_MSK2_Pos (15U)
11513 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
11514 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11515 #define RTC_ALRMBR_MNT_Pos (12U)
11516 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
11517 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11518 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
11519 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
11520 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
11521 #define RTC_ALRMBR_MNU_Pos (8U)
11522 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
11523 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11524 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
11525 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
11526 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
11527 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
11528 #define RTC_ALRMBR_MSK1_Pos (7U)
11529 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
11530 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11531 #define RTC_ALRMBR_ST_Pos (4U)
11532 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
11533 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11534 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
11535 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
11536 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
11537 #define RTC_ALRMBR_SU_Pos (0U)
11538 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
11539 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11540 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
11541 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
11542 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
11543 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
11545 /******************** Bits definition for RTC_WPR register ******************/
11546 #define RTC_WPR_KEY_Pos (0U)
11547 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
11548 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
11549 
11550 /******************** Bits definition for RTC_SSR register ******************/
11551 #define RTC_SSR_SS_Pos (0U)
11552 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
11553 #define RTC_SSR_SS RTC_SSR_SS_Msk
11554 
11555 /******************** Bits definition for RTC_SHIFTR register ***************/
11556 #define RTC_SHIFTR_SUBFS_Pos (0U)
11557 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
11558 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11559 #define RTC_SHIFTR_ADD1S_Pos (31U)
11560 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
11561 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11562 
11563 /******************** Bits definition for RTC_TSTR register *****************/
11564 #define RTC_TSTR_PM_Pos (22U)
11565 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
11566 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
11567 #define RTC_TSTR_HT_Pos (20U)
11568 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
11569 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
11570 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
11571 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
11572 #define RTC_TSTR_HU_Pos (16U)
11573 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
11574 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
11575 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
11576 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
11577 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
11578 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
11579 #define RTC_TSTR_MNT_Pos (12U)
11580 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
11581 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11582 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
11583 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
11584 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
11585 #define RTC_TSTR_MNU_Pos (8U)
11586 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
11587 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11588 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
11589 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
11590 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
11591 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
11592 #define RTC_TSTR_ST_Pos (4U)
11593 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
11594 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
11595 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
11596 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
11597 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
11598 #define RTC_TSTR_SU_Pos (0U)
11599 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
11600 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
11601 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
11602 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
11603 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
11604 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
11606 /******************** Bits definition for RTC_TSDR register *****************/
11607 #define RTC_TSDR_WDU_Pos (13U)
11608 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
11609 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11610 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
11611 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
11612 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
11613 #define RTC_TSDR_MT_Pos (12U)
11614 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
11615 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
11616 #define RTC_TSDR_MU_Pos (8U)
11617 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
11618 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
11619 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
11620 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
11621 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
11622 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
11623 #define RTC_TSDR_DT_Pos (4U)
11624 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
11625 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
11626 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
11627 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
11628 #define RTC_TSDR_DU_Pos (0U)
11629 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
11630 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
11631 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
11632 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
11633 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
11634 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
11636 /******************** Bits definition for RTC_TSSSR register ****************/
11637 #define RTC_TSSSR_SS_Pos (0U)
11638 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
11639 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11640 
11641 /******************** Bits definition for RTC_CAL register *****************/
11642 #define RTC_CALR_CALP_Pos (15U)
11643 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
11644 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
11645 #define RTC_CALR_CALW8_Pos (14U)
11646 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
11647 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11648 #define RTC_CALR_CALW16_Pos (13U)
11649 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
11650 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11651 #define RTC_CALR_CALM_Pos (0U)
11652 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
11653 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
11654 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
11655 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
11656 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
11657 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
11658 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
11659 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
11660 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
11661 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
11662 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
11664 /******************** Bits definition for RTC_TAFCR register ****************/
11665 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
11666 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
11667 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
11668 #define RTC_TAFCR_TSINSEL_Pos (17U)
11669 #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
11670 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
11671 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
11672 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
11673 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
11674 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
11675 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
11676 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
11677 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
11678 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
11679 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
11680 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
11681 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
11682 #define RTC_TAFCR_TAMPFLT_Pos (11U)
11683 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
11684 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
11685 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
11686 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
11687 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
11688 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
11689 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
11690 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
11691 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
11692 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
11693 #define RTC_TAFCR_TAMPTS_Pos (7U)
11694 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
11695 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
11696 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
11697 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
11698 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
11699 #define RTC_TAFCR_TAMP2E_Pos (3U)
11700 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
11701 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
11702 #define RTC_TAFCR_TAMPIE_Pos (2U)
11703 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
11704 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
11705 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
11706 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
11707 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
11708 #define RTC_TAFCR_TAMP1E_Pos (0U)
11709 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
11710 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
11711 
11712 /* Legacy defines */
11713 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
11714 
11715 /******************** Bits definition for RTC_ALRMASSR register *************/
11716 #define RTC_ALRMASSR_MASKSS_Pos (24U)
11717 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
11718 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
11719 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
11720 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
11721 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
11722 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
11723 #define RTC_ALRMASSR_SS_Pos (0U)
11724 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
11725 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
11726 
11727 /******************** Bits definition for RTC_ALRMBSSR register *************/
11728 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
11729 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
11730 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11731 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
11732 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
11733 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
11734 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
11735 #define RTC_ALRMBSSR_SS_Pos (0U)
11736 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
11737 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11738 
11739 /******************** Bits definition for RTC_BKP0R register ****************/
11740 #define RTC_BKP0R_Pos (0U)
11741 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
11742 #define RTC_BKP0R RTC_BKP0R_Msk
11743 
11744 /******************** Bits definition for RTC_BKP1R register ****************/
11745 #define RTC_BKP1R_Pos (0U)
11746 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
11747 #define RTC_BKP1R RTC_BKP1R_Msk
11748 
11749 /******************** Bits definition for RTC_BKP2R register ****************/
11750 #define RTC_BKP2R_Pos (0U)
11751 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
11752 #define RTC_BKP2R RTC_BKP2R_Msk
11753 
11754 /******************** Bits definition for RTC_BKP3R register ****************/
11755 #define RTC_BKP3R_Pos (0U)
11756 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
11757 #define RTC_BKP3R RTC_BKP3R_Msk
11758 
11759 /******************** Bits definition for RTC_BKP4R register ****************/
11760 #define RTC_BKP4R_Pos (0U)
11761 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
11762 #define RTC_BKP4R RTC_BKP4R_Msk
11763 
11764 /******************** Bits definition for RTC_BKP5R register ****************/
11765 #define RTC_BKP5R_Pos (0U)
11766 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
11767 #define RTC_BKP5R RTC_BKP5R_Msk
11768 
11769 /******************** Bits definition for RTC_BKP6R register ****************/
11770 #define RTC_BKP6R_Pos (0U)
11771 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
11772 #define RTC_BKP6R RTC_BKP6R_Msk
11773 
11774 /******************** Bits definition for RTC_BKP7R register ****************/
11775 #define RTC_BKP7R_Pos (0U)
11776 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
11777 #define RTC_BKP7R RTC_BKP7R_Msk
11778 
11779 /******************** Bits definition for RTC_BKP8R register ****************/
11780 #define RTC_BKP8R_Pos (0U)
11781 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
11782 #define RTC_BKP8R RTC_BKP8R_Msk
11783 
11784 /******************** Bits definition for RTC_BKP9R register ****************/
11785 #define RTC_BKP9R_Pos (0U)
11786 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
11787 #define RTC_BKP9R RTC_BKP9R_Msk
11788 
11789 /******************** Bits definition for RTC_BKP10R register ***************/
11790 #define RTC_BKP10R_Pos (0U)
11791 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
11792 #define RTC_BKP10R RTC_BKP10R_Msk
11793 
11794 /******************** Bits definition for RTC_BKP11R register ***************/
11795 #define RTC_BKP11R_Pos (0U)
11796 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
11797 #define RTC_BKP11R RTC_BKP11R_Msk
11798 
11799 /******************** Bits definition for RTC_BKP12R register ***************/
11800 #define RTC_BKP12R_Pos (0U)
11801 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
11802 #define RTC_BKP12R RTC_BKP12R_Msk
11803 
11804 /******************** Bits definition for RTC_BKP13R register ***************/
11805 #define RTC_BKP13R_Pos (0U)
11806 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
11807 #define RTC_BKP13R RTC_BKP13R_Msk
11808 
11809 /******************** Bits definition for RTC_BKP14R register ***************/
11810 #define RTC_BKP14R_Pos (0U)
11811 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
11812 #define RTC_BKP14R RTC_BKP14R_Msk
11813 
11814 /******************** Bits definition for RTC_BKP15R register ***************/
11815 #define RTC_BKP15R_Pos (0U)
11816 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
11817 #define RTC_BKP15R RTC_BKP15R_Msk
11818 
11819 /******************** Bits definition for RTC_BKP16R register ***************/
11820 #define RTC_BKP16R_Pos (0U)
11821 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
11822 #define RTC_BKP16R RTC_BKP16R_Msk
11823 
11824 /******************** Bits definition for RTC_BKP17R register ***************/
11825 #define RTC_BKP17R_Pos (0U)
11826 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
11827 #define RTC_BKP17R RTC_BKP17R_Msk
11828 
11829 /******************** Bits definition for RTC_BKP18R register ***************/
11830 #define RTC_BKP18R_Pos (0U)
11831 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
11832 #define RTC_BKP18R RTC_BKP18R_Msk
11833 
11834 /******************** Bits definition for RTC_BKP19R register ***************/
11835 #define RTC_BKP19R_Pos (0U)
11836 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
11837 #define RTC_BKP19R RTC_BKP19R_Msk
11838 
11839 /******************** Number of backup registers ******************************/
11840 #define RTC_BKP_NUMBER 0x000000014U
11841 
11842 /******************************************************************************/
11843 /* */
11844 /* Serial Audio Interface */
11845 /* */
11846 /******************************************************************************/
11847 /******************** Bit definition for SAI_GCR register *******************/
11848 #define SAI_GCR_SYNCIN_Pos (0U)
11849 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
11850 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
11851 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
11852 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
11854 #define SAI_GCR_SYNCOUT_Pos (4U)
11855 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
11856 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
11857 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
11858 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
11860 /******************* Bit definition for SAI_xCR1 register *******************/
11861 #define SAI_xCR1_MODE_Pos (0U)
11862 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
11863 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
11864 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
11865 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
11867 #define SAI_xCR1_PRTCFG_Pos (2U)
11868 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
11869 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
11870 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
11871 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
11873 #define SAI_xCR1_DS_Pos (5U)
11874 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
11875 #define SAI_xCR1_DS SAI_xCR1_DS_Msk
11876 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
11877 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
11878 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
11880 #define SAI_xCR1_LSBFIRST_Pos (8U)
11881 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
11882 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
11883 #define SAI_xCR1_CKSTR_Pos (9U)
11884 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
11885 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
11887 #define SAI_xCR1_SYNCEN_Pos (10U)
11888 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
11889 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
11890 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
11891 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
11893 #define SAI_xCR1_MONO_Pos (12U)
11894 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
11895 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
11896 #define SAI_xCR1_OUTDRIV_Pos (13U)
11897 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
11898 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
11899 #define SAI_xCR1_SAIEN_Pos (16U)
11900 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
11901 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
11902 #define SAI_xCR1_DMAEN_Pos (17U)
11903 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
11904 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
11905 #define SAI_xCR1_NODIV_Pos (19U)
11906 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
11907 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
11909 #define SAI_xCR1_MCKDIV_Pos (20U)
11910 #define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
11911 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
11912 #define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
11913 #define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
11914 #define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
11915 #define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
11917 /******************* Bit definition for SAI_xCR2 register *******************/
11918 #define SAI_xCR2_FTH_Pos (0U)
11919 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
11920 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
11921 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
11922 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
11923 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
11925 #define SAI_xCR2_FFLUSH_Pos (3U)
11926 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
11927 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
11928 #define SAI_xCR2_TRIS_Pos (4U)
11929 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
11930 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
11931 #define SAI_xCR2_MUTE_Pos (5U)
11932 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
11933 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
11934 #define SAI_xCR2_MUTEVAL_Pos (6U)
11935 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
11936 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
11938 #define SAI_xCR2_MUTECNT_Pos (7U)
11939 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
11940 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
11941 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
11942 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
11943 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
11944 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
11945 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
11946 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
11948 #define SAI_xCR2_CPL_Pos (13U)
11949 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
11950 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
11952 #define SAI_xCR2_COMP_Pos (14U)
11953 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
11954 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
11955 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
11956 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
11958 /****************** Bit definition for SAI_xFRCR register *******************/
11959 #define SAI_xFRCR_FRL_Pos (0U)
11960 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
11961 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
11962 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
11963 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
11964 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
11965 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
11966 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
11967 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
11968 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
11969 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
11971 #define SAI_xFRCR_FSALL_Pos (8U)
11972 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
11973 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
11974 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
11975 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
11976 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
11977 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
11978 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
11979 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
11980 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
11982 #define SAI_xFRCR_FSDEF_Pos (16U)
11983 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
11984 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
11985 #define SAI_xFRCR_FSPOL_Pos (17U)
11986 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
11987 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
11988 #define SAI_xFRCR_FSOFF_Pos (18U)
11989 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
11990 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
11991 /* Legacy defines */
11992 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
11993 
11994 /****************** Bit definition for SAI_xSLOTR register *******************/
11995 #define SAI_xSLOTR_FBOFF_Pos (0U)
11996 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
11997 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
11998 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
11999 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12000 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12001 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12002 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12004 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
12005 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12006 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12007 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12008 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12010 #define SAI_xSLOTR_NBSLOT_Pos (8U)
12011 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12012 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12013 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12014 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12015 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12016 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12018 #define SAI_xSLOTR_SLOTEN_Pos (16U)
12019 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12020 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12022 /******************* Bit definition for SAI_xIMR register *******************/
12023 #define SAI_xIMR_OVRUDRIE_Pos (0U)
12024 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12025 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12026 #define SAI_xIMR_MUTEDETIE_Pos (1U)
12027 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12028 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12029 #define SAI_xIMR_WCKCFGIE_Pos (2U)
12030 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12031 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12032 #define SAI_xIMR_FREQIE_Pos (3U)
12033 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12034 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12035 #define SAI_xIMR_CNRDYIE_Pos (4U)
12036 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12037 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12038 #define SAI_xIMR_AFSDETIE_Pos (5U)
12039 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12040 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12041 #define SAI_xIMR_LFSDETIE_Pos (6U)
12042 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12043 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12045 /******************** Bit definition for SAI_xSR register *******************/
12046 #define SAI_xSR_OVRUDR_Pos (0U)
12047 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12048 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12049 #define SAI_xSR_MUTEDET_Pos (1U)
12050 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12051 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12052 #define SAI_xSR_WCKCFG_Pos (2U)
12053 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12054 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12055 #define SAI_xSR_FREQ_Pos (3U)
12056 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12057 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12058 #define SAI_xSR_CNRDY_Pos (4U)
12059 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12060 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12061 #define SAI_xSR_AFSDET_Pos (5U)
12062 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12063 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12064 #define SAI_xSR_LFSDET_Pos (6U)
12065 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12066 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12068 #define SAI_xSR_FLVL_Pos (16U)
12069 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12070 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12071 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12072 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12073 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12075 /****************** Bit definition for SAI_xCLRFR register ******************/
12076 #define SAI_xCLRFR_COVRUDR_Pos (0U)
12077 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12078 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12079 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
12080 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12081 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12082 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
12083 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12084 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12085 #define SAI_xCLRFR_CFREQ_Pos (3U)
12086 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12087 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12088 #define SAI_xCLRFR_CCNRDY_Pos (4U)
12089 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12090 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12091 #define SAI_xCLRFR_CAFSDET_Pos (5U)
12092 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12093 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12094 #define SAI_xCLRFR_CLFSDET_Pos (6U)
12095 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12096 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12098 /****************** Bit definition for SAI_xDR register ******************/
12099 #define SAI_xDR_DATA_Pos (0U)
12100 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12101 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
12102 
12103 /******************************************************************************/
12104 /* */
12105 /* SPDIF-RX Interface */
12106 /* */
12107 /******************************************************************************/
12108 /******************** Bit definition for SPDIFRX_CR register *******************/
12109 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
12110 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
12111 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
12112 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
12113 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
12114 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
12115 #define SPDIFRX_CR_RXSTEO_Pos (3U)
12116 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
12117 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
12118 #define SPDIFRX_CR_DRFMT_Pos (4U)
12119 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
12120 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
12121 #define SPDIFRX_CR_PMSK_Pos (6U)
12122 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
12123 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
12124 #define SPDIFRX_CR_VMSK_Pos (7U)
12125 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
12126 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
12127 #define SPDIFRX_CR_CUMSK_Pos (8U)
12128 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
12129 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
12130 #define SPDIFRX_CR_PTMSK_Pos (9U)
12131 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
12132 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
12133 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
12134 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
12135 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
12136 #define SPDIFRX_CR_CHSEL_Pos (11U)
12137 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
12138 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
12139 #define SPDIFRX_CR_NBTR_Pos (12U)
12140 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
12141 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
12142 #define SPDIFRX_CR_WFA_Pos (14U)
12143 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
12144 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
12145 #define SPDIFRX_CR_INSEL_Pos (16U)
12146 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
12147 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
12149 /******************* Bit definition for SPDIFRX_IMR register *******************/
12150 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
12151 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
12152 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
12153 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
12154 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
12155 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
12156 #define SPDIFRX_IMR_PERRIE_Pos (2U)
12157 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
12158 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
12159 #define SPDIFRX_IMR_OVRIE_Pos (3U)
12160 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
12161 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
12162 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
12163 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
12164 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
12165 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
12166 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
12167 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
12168 #define SPDIFRX_IMR_IFEIE_Pos (6U)
12169 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
12170 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
12172 /******************* Bit definition for SPDIFRX_SR register *******************/
12173 #define SPDIFRX_SR_RXNE_Pos (0U)
12174 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
12175 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
12176 #define SPDIFRX_SR_CSRNE_Pos (1U)
12177 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
12178 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
12179 #define SPDIFRX_SR_PERR_Pos (2U)
12180 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
12181 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
12182 #define SPDIFRX_SR_OVR_Pos (3U)
12183 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
12184 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
12185 #define SPDIFRX_SR_SBD_Pos (4U)
12186 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
12187 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
12188 #define SPDIFRX_SR_SYNCD_Pos (5U)
12189 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
12190 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
12191 #define SPDIFRX_SR_FERR_Pos (6U)
12192 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
12193 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
12194 #define SPDIFRX_SR_SERR_Pos (7U)
12195 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
12196 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
12197 #define SPDIFRX_SR_TERR_Pos (8U)
12198 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
12199 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
12200 #define SPDIFRX_SR_WIDTH5_Pos (16U)
12201 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
12202 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
12204 /******************* Bit definition for SPDIFRX_IFCR register *******************/
12205 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
12206 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
12207 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
12208 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
12209 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
12210 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
12211 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
12212 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
12213 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
12214 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
12215 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
12216 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
12218 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
12219 #define SPDIFRX_DR0_DR_Pos (0U)
12220 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
12221 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
12222 #define SPDIFRX_DR0_PE_Pos (24U)
12223 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
12224 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
12225 #define SPDIFRX_DR0_V_Pos (25U)
12226 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
12227 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
12228 #define SPDIFRX_DR0_U_Pos (26U)
12229 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
12230 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
12231 #define SPDIFRX_DR0_C_Pos (27U)
12232 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
12233 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
12234 #define SPDIFRX_DR0_PT_Pos (28U)
12235 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
12236 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
12238 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
12239 #define SPDIFRX_DR1_DR_Pos (8U)
12240 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
12241 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
12242 #define SPDIFRX_DR1_PT_Pos (4U)
12243 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
12244 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
12245 #define SPDIFRX_DR1_C_Pos (3U)
12246 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
12247 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
12248 #define SPDIFRX_DR1_U_Pos (2U)
12249 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
12250 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
12251 #define SPDIFRX_DR1_V_Pos (1U)
12252 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
12253 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
12254 #define SPDIFRX_DR1_PE_Pos (0U)
12255 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
12256 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
12258 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
12259 #define SPDIFRX_DR1_DRNL1_Pos (16U)
12260 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
12261 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
12262 #define SPDIFRX_DR1_DRNL2_Pos (0U)
12263 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
12264 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
12266 /******************* Bit definition for SPDIFRX_CSR register *******************/
12267 #define SPDIFRX_CSR_USR_Pos (0U)
12268 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
12269 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
12270 #define SPDIFRX_CSR_CS_Pos (16U)
12271 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
12272 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
12273 #define SPDIFRX_CSR_SOB_Pos (24U)
12274 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
12275 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
12277 /******************* Bit definition for SPDIFRX_DIR register *******************/
12278 #define SPDIFRX_DIR_THI_Pos (0U)
12279 #define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos)
12280 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
12281 #define SPDIFRX_DIR_TLO_Pos (16U)
12282 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
12283 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
12286 /******************************************************************************/
12287 /* */
12288 /* SD host Interface */
12289 /* */
12290 /******************************************************************************/
12291 /****************** Bit definition for SDIO_POWER register ******************/
12292 #define SDIO_POWER_PWRCTRL_Pos (0U)
12293 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
12294 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
12295 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
12296 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
12298 /****************** Bit definition for SDIO_CLKCR register ******************/
12299 #define SDIO_CLKCR_CLKDIV_Pos (0U)
12300 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
12301 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
12302 #define SDIO_CLKCR_CLKEN_Pos (8U)
12303 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
12304 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
12305 #define SDIO_CLKCR_PWRSAV_Pos (9U)
12306 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
12307 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
12308 #define SDIO_CLKCR_BYPASS_Pos (10U)
12309 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
12310 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
12312 #define SDIO_CLKCR_WIDBUS_Pos (11U)
12313 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
12314 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
12315 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
12316 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
12318 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
12319 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
12320 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
12321 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
12322 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
12323 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
12325 /******************* Bit definition for SDIO_ARG register *******************/
12326 #define SDIO_ARG_CMDARG_Pos (0U)
12327 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
12328 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
12330 /******************* Bit definition for SDIO_CMD register *******************/
12331 #define SDIO_CMD_CMDINDEX_Pos (0U)
12332 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
12333 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
12335 #define SDIO_CMD_WAITRESP_Pos (6U)
12336 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
12337 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
12338 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
12339 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
12341 #define SDIO_CMD_WAITINT_Pos (8U)
12342 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
12343 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
12344 #define SDIO_CMD_WAITPEND_Pos (9U)
12345 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
12346 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
12347 #define SDIO_CMD_CPSMEN_Pos (10U)
12348 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
12349 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
12350 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
12351 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
12352 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
12354 /***************** Bit definition for SDIO_RESPCMD register *****************/
12355 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
12356 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
12357 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
12359 /****************** Bit definition for SDIO_RESP0 register ******************/
12360 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
12361 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
12362 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
12364 /****************** Bit definition for SDIO_RESP1 register ******************/
12365 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
12366 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
12367 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
12369 /****************** Bit definition for SDIO_RESP2 register ******************/
12370 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
12371 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
12372 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
12374 /****************** Bit definition for SDIO_RESP3 register ******************/
12375 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
12376 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
12377 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
12379 /****************** Bit definition for SDIO_RESP4 register ******************/
12380 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
12381 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
12382 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
12384 /****************** Bit definition for SDIO_DTIMER register *****************/
12385 #define SDIO_DTIMER_DATATIME_Pos (0U)
12386 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
12387 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
12389 /****************** Bit definition for SDIO_DLEN register *******************/
12390 #define SDIO_DLEN_DATALENGTH_Pos (0U)
12391 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
12392 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
12394 /****************** Bit definition for SDIO_DCTRL register ******************/
12395 #define SDIO_DCTRL_DTEN_Pos (0U)
12396 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
12397 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
12398 #define SDIO_DCTRL_DTDIR_Pos (1U)
12399 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
12400 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
12401 #define SDIO_DCTRL_DTMODE_Pos (2U)
12402 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
12403 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
12404 #define SDIO_DCTRL_DMAEN_Pos (3U)
12405 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
12406 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
12408 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
12409 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12410 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
12411 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12412 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12413 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12414 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
12416 #define SDIO_DCTRL_RWSTART_Pos (8U)
12417 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
12418 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
12419 #define SDIO_DCTRL_RWSTOP_Pos (9U)
12420 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
12421 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
12422 #define SDIO_DCTRL_RWMOD_Pos (10U)
12423 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
12424 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
12425 #define SDIO_DCTRL_SDIOEN_Pos (11U)
12426 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
12427 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
12429 /****************** Bit definition for SDIO_DCOUNT register *****************/
12430 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
12431 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
12432 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
12434 /****************** Bit definition for SDIO_STA register ********************/
12435 #define SDIO_STA_CCRCFAIL_Pos (0U)
12436 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
12437 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
12438 #define SDIO_STA_DCRCFAIL_Pos (1U)
12439 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
12440 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
12441 #define SDIO_STA_CTIMEOUT_Pos (2U)
12442 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
12443 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
12444 #define SDIO_STA_DTIMEOUT_Pos (3U)
12445 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
12446 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
12447 #define SDIO_STA_TXUNDERR_Pos (4U)
12448 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
12449 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
12450 #define SDIO_STA_RXOVERR_Pos (5U)
12451 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
12452 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
12453 #define SDIO_STA_CMDREND_Pos (6U)
12454 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
12455 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
12456 #define SDIO_STA_CMDSENT_Pos (7U)
12457 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
12458 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
12459 #define SDIO_STA_DATAEND_Pos (8U)
12460 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
12461 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
12462 #define SDIO_STA_DBCKEND_Pos (10U)
12463 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
12464 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
12465 #define SDIO_STA_CMDACT_Pos (11U)
12466 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
12467 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
12468 #define SDIO_STA_TXACT_Pos (12U)
12469 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
12470 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
12471 #define SDIO_STA_RXACT_Pos (13U)
12472 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
12473 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
12474 #define SDIO_STA_TXFIFOHE_Pos (14U)
12475 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
12476 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
12477 #define SDIO_STA_RXFIFOHF_Pos (15U)
12478 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
12479 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
12480 #define SDIO_STA_TXFIFOF_Pos (16U)
12481 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
12482 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
12483 #define SDIO_STA_RXFIFOF_Pos (17U)
12484 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
12485 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
12486 #define SDIO_STA_TXFIFOE_Pos (18U)
12487 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
12488 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
12489 #define SDIO_STA_RXFIFOE_Pos (19U)
12490 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
12491 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
12492 #define SDIO_STA_TXDAVL_Pos (20U)
12493 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
12494 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
12495 #define SDIO_STA_RXDAVL_Pos (21U)
12496 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
12497 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
12498 #define SDIO_STA_SDIOIT_Pos (22U)
12499 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
12500 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
12502 /******************* Bit definition for SDIO_ICR register *******************/
12503 #define SDIO_ICR_CCRCFAILC_Pos (0U)
12504 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
12505 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
12506 #define SDIO_ICR_DCRCFAILC_Pos (1U)
12507 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
12508 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
12509 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
12510 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
12511 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
12512 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
12513 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
12514 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
12515 #define SDIO_ICR_TXUNDERRC_Pos (4U)
12516 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
12517 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
12518 #define SDIO_ICR_RXOVERRC_Pos (5U)
12519 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
12520 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
12521 #define SDIO_ICR_CMDRENDC_Pos (6U)
12522 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
12523 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
12524 #define SDIO_ICR_CMDSENTC_Pos (7U)
12525 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
12526 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
12527 #define SDIO_ICR_DATAENDC_Pos (8U)
12528 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
12529 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
12530 #define SDIO_ICR_DBCKENDC_Pos (10U)
12531 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
12532 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
12533 #define SDIO_ICR_SDIOITC_Pos (22U)
12534 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
12535 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
12537 /****************** Bit definition for SDIO_MASK register *******************/
12538 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
12539 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
12540 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
12541 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
12542 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
12543 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
12544 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
12545 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
12546 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
12547 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
12548 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
12549 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
12550 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
12551 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
12552 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
12553 #define SDIO_MASK_RXOVERRIE_Pos (5U)
12554 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
12555 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
12556 #define SDIO_MASK_CMDRENDIE_Pos (6U)
12557 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
12558 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
12559 #define SDIO_MASK_CMDSENTIE_Pos (7U)
12560 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
12561 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
12562 #define SDIO_MASK_DATAENDIE_Pos (8U)
12563 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
12564 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
12565 #define SDIO_MASK_DBCKENDIE_Pos (10U)
12566 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
12567 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
12568 #define SDIO_MASK_CMDACTIE_Pos (11U)
12569 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
12570 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
12571 #define SDIO_MASK_TXACTIE_Pos (12U)
12572 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
12573 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
12574 #define SDIO_MASK_RXACTIE_Pos (13U)
12575 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
12576 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
12577 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
12578 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
12579 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
12580 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
12581 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
12582 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
12583 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
12584 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
12585 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
12586 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
12587 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
12588 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
12589 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
12590 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
12591 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
12592 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
12593 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
12594 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
12595 #define SDIO_MASK_TXDAVLIE_Pos (20U)
12596 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
12597 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
12598 #define SDIO_MASK_RXDAVLIE_Pos (21U)
12599 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
12600 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
12601 #define SDIO_MASK_SDIOITIE_Pos (22U)
12602 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
12603 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
12605 /***************** Bit definition for SDIO_FIFOCNT register *****************/
12606 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
12607 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
12608 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
12610 /****************** Bit definition for SDIO_FIFO register *******************/
12611 #define SDIO_FIFO_FIFODATA_Pos (0U)
12612 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
12613 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
12615 /******************************************************************************/
12616 /* */
12617 /* Serial Peripheral Interface */
12618 /* */
12619 /******************************************************************************/
12620 #define I2S_APB1_APB2_FEATURE
12622 /******************* Bit definition for SPI_CR1 register ********************/
12623 #define SPI_CR1_CPHA_Pos (0U)
12624 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
12625 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
12626 #define SPI_CR1_CPOL_Pos (1U)
12627 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
12628 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
12629 #define SPI_CR1_MSTR_Pos (2U)
12630 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
12631 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
12633 #define SPI_CR1_BR_Pos (3U)
12634 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
12635 #define SPI_CR1_BR SPI_CR1_BR_Msk
12636 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
12637 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
12638 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
12640 #define SPI_CR1_SPE_Pos (6U)
12641 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
12642 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
12643 #define SPI_CR1_LSBFIRST_Pos (7U)
12644 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
12645 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
12646 #define SPI_CR1_SSI_Pos (8U)
12647 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
12648 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
12649 #define SPI_CR1_SSM_Pos (9U)
12650 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
12651 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
12652 #define SPI_CR1_RXONLY_Pos (10U)
12653 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
12654 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
12655 #define SPI_CR1_DFF_Pos (11U)
12656 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
12657 #define SPI_CR1_DFF SPI_CR1_DFF_Msk
12658 #define SPI_CR1_CRCNEXT_Pos (12U)
12659 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
12660 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
12661 #define SPI_CR1_CRCEN_Pos (13U)
12662 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
12663 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
12664 #define SPI_CR1_BIDIOE_Pos (14U)
12665 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
12666 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
12667 #define SPI_CR1_BIDIMODE_Pos (15U)
12668 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
12669 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
12671 /******************* Bit definition for SPI_CR2 register ********************/
12672 #define SPI_CR2_RXDMAEN_Pos (0U)
12673 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
12674 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
12675 #define SPI_CR2_TXDMAEN_Pos (1U)
12676 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
12677 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
12678 #define SPI_CR2_SSOE_Pos (2U)
12679 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
12680 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
12681 #define SPI_CR2_FRF_Pos (4U)
12682 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
12683 #define SPI_CR2_FRF SPI_CR2_FRF_Msk
12684 #define SPI_CR2_ERRIE_Pos (5U)
12685 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
12686 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
12687 #define SPI_CR2_RXNEIE_Pos (6U)
12688 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
12689 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
12690 #define SPI_CR2_TXEIE_Pos (7U)
12691 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
12692 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
12694 /******************** Bit definition for SPI_SR register ********************/
12695 #define SPI_SR_RXNE_Pos (0U)
12696 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
12697 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
12698 #define SPI_SR_TXE_Pos (1U)
12699 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
12700 #define SPI_SR_TXE SPI_SR_TXE_Msk
12701 #define SPI_SR_CHSIDE_Pos (2U)
12702 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
12703 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
12704 #define SPI_SR_UDR_Pos (3U)
12705 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
12706 #define SPI_SR_UDR SPI_SR_UDR_Msk
12707 #define SPI_SR_CRCERR_Pos (4U)
12708 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
12709 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
12710 #define SPI_SR_MODF_Pos (5U)
12711 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
12712 #define SPI_SR_MODF SPI_SR_MODF_Msk
12713 #define SPI_SR_OVR_Pos (6U)
12714 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
12715 #define SPI_SR_OVR SPI_SR_OVR_Msk
12716 #define SPI_SR_BSY_Pos (7U)
12717 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
12718 #define SPI_SR_BSY SPI_SR_BSY_Msk
12719 #define SPI_SR_FRE_Pos (8U)
12720 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
12721 #define SPI_SR_FRE SPI_SR_FRE_Msk
12723 /******************** Bit definition for SPI_DR register ********************/
12724 #define SPI_DR_DR_Pos (0U)
12725 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
12726 #define SPI_DR_DR SPI_DR_DR_Msk
12728 /******************* Bit definition for SPI_CRCPR register ******************/
12729 #define SPI_CRCPR_CRCPOLY_Pos (0U)
12730 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
12731 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
12733 /****************** Bit definition for SPI_RXCRCR register ******************/
12734 #define SPI_RXCRCR_RXCRC_Pos (0U)
12735 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
12736 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
12738 /****************** Bit definition for SPI_TXCRCR register ******************/
12739 #define SPI_TXCRCR_TXCRC_Pos (0U)
12740 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
12741 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
12743 /****************** Bit definition for SPI_I2SCFGR register *****************/
12744 #define SPI_I2SCFGR_CHLEN_Pos (0U)
12745 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
12746 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
12748 #define SPI_I2SCFGR_DATLEN_Pos (1U)
12749 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
12750 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
12751 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
12752 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
12754 #define SPI_I2SCFGR_CKPOL_Pos (3U)
12755 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
12756 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
12758 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
12759 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
12760 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
12761 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
12762 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
12764 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12765 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
12766 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
12768 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
12769 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
12770 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
12771 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
12772 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
12774 #define SPI_I2SCFGR_I2SE_Pos (10U)
12775 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
12776 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
12777 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
12778 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
12779 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
12780 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
12781 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
12782 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
12784 /****************** Bit definition for SPI_I2SPR register *******************/
12785 #define SPI_I2SPR_I2SDIV_Pos (0U)
12786 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
12787 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
12788 #define SPI_I2SPR_ODD_Pos (8U)
12789 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
12790 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
12791 #define SPI_I2SPR_MCKOE_Pos (9U)
12792 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
12793 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
12795 /******************************************************************************/
12796 /* */
12797 /* SYSCFG */
12798 /* */
12799 /******************************************************************************/
12800 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
12801 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
12802 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12803 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
12804 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12805 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12806 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12807 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
12808 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos)
12809 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk
12810 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
12811 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
12812 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
12813 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
12814 /* Legacy Defines */
12815 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
12816 /****************** Bit definition for SYSCFG_PMC register ******************/
12817 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
12818 #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
12819 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
12820 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
12821 #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
12822 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
12823 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
12824 #define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
12825 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
12826 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
12827 #define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
12828 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
12830 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12831 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12832 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
12833 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
12834 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12835 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
12836 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
12837 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12838 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
12839 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
12840 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12841 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
12842 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
12846 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
12847 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
12848 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
12849 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
12850 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
12851 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
12852 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
12853 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
12854 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
12855 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
12856 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
12861 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
12862 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
12863 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
12864 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
12865 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
12866 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
12867 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
12868 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
12869 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
12870 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
12871 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
12876 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
12877 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
12878 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
12879 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
12880 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
12881 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
12882 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
12883 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
12884 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
12885 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
12886 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
12891 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
12892 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
12893 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
12894 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
12895 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
12896 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
12897 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
12898 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
12899 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
12900 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
12901 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
12903 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12904 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12905 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
12906 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
12907 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12908 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
12909 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
12910 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12911 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
12912 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
12913 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12914 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
12915 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
12920 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
12921 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
12922 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
12923 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
12924 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
12925 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
12926 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
12927 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
12928 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
12929 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
12930 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
12935 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
12936 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
12937 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
12938 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
12939 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
12940 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
12941 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
12942 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
12943 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
12944 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
12945 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
12950 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
12951 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
12952 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
12953 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
12954 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
12955 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
12956 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
12957 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
12958 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
12959 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
12960 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
12965 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
12966 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
12967 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
12968 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
12969 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
12970 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
12971 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
12972 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
12973 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
12974 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
12975 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
12977 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12978 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12979 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
12980 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
12981 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12982 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
12983 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
12984 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12985 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
12986 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
12987 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12988 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
12989 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
12994 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
12995 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
12996 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
12997 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
12998 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
12999 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
13000 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
13001 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
13002 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
13003 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
13008 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
13009 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
13010 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
13011 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
13012 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
13013 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
13014 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
13015 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
13016 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
13017 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
13022 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
13023 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
13024 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
13025 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
13026 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
13027 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
13028 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
13029 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
13030 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
13031 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
13036 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
13037 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
13038 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
13039 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
13040 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
13041 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
13042 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
13043 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
13044 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
13045 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
13048 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13049 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13050 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
13051 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13052 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13053 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
13054 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13055 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13056 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
13057 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13058 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13059 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
13060 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13065 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
13066 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
13067 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
13068 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
13069 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
13070 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
13071 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
13072 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
13073 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
13074 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
13079 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
13080 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
13081 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
13082 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
13083 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
13084 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
13085 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
13086 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
13087 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
13088 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
13093 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
13094 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
13095 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
13096 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
13097 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
13098 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
13099 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
13100 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
13101 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
13102 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
13107 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
13108 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
13109 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
13110 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
13111 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
13112 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
13113 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
13114 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
13115 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
13116 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
13118 /****************** Bit definition for SYSCFG_CMPCR register ****************/
13119 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13120 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
13121 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
13122 #define SYSCFG_CMPCR_READY_Pos (8U)
13123 #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
13124 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
13125 /****************** Bit definition for SYSCFG_CFGR register ****************/
13126 #define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
13127 #define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos)
13128 #define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk
13129 #define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
13130 #define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos)
13131 #define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk
13134 /******************************************************************************/
13135 /* */
13136 /* TIM */
13137 /* */
13138 /******************************************************************************/
13139 /******************* Bit definition for TIM_CR1 register ********************/
13140 #define TIM_CR1_CEN_Pos (0U)
13141 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13142 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
13143 #define TIM_CR1_UDIS_Pos (1U)
13144 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13145 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13146 #define TIM_CR1_URS_Pos (2U)
13147 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13148 #define TIM_CR1_URS TIM_CR1_URS_Msk
13149 #define TIM_CR1_OPM_Pos (3U)
13150 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13151 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
13152 #define TIM_CR1_DIR_Pos (4U)
13153 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13154 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
13156 #define TIM_CR1_CMS_Pos (5U)
13157 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13158 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
13159 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13160 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13162 #define TIM_CR1_ARPE_Pos (7U)
13163 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13164 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13166 #define TIM_CR1_CKD_Pos (8U)
13167 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13168 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
13169 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13170 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13172 /******************* Bit definition for TIM_CR2 register ********************/
13173 #define TIM_CR2_CCPC_Pos (0U)
13174 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
13175 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
13176 #define TIM_CR2_CCUS_Pos (2U)
13177 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
13178 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
13179 #define TIM_CR2_CCDS_Pos (3U)
13180 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
13181 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
13183 #define TIM_CR2_MMS_Pos (4U)
13184 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
13185 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
13186 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
13187 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
13188 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
13190 #define TIM_CR2_TI1S_Pos (7U)
13191 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
13192 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
13193 #define TIM_CR2_OIS1_Pos (8U)
13194 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
13195 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
13196 #define TIM_CR2_OIS1N_Pos (9U)
13197 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
13198 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
13199 #define TIM_CR2_OIS2_Pos (10U)
13200 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
13201 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
13202 #define TIM_CR2_OIS2N_Pos (11U)
13203 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
13204 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
13205 #define TIM_CR2_OIS3_Pos (12U)
13206 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
13207 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
13208 #define TIM_CR2_OIS3N_Pos (13U)
13209 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
13210 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
13211 #define TIM_CR2_OIS4_Pos (14U)
13212 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
13213 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
13215 /******************* Bit definition for TIM_SMCR register *******************/
13216 #define TIM_SMCR_SMS_Pos (0U)
13217 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
13218 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
13219 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
13220 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
13221 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
13223 #define TIM_SMCR_TS_Pos (4U)
13224 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
13225 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
13226 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
13227 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
13228 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
13230 #define TIM_SMCR_MSM_Pos (7U)
13231 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
13232 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
13234 #define TIM_SMCR_ETF_Pos (8U)
13235 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
13236 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
13237 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
13238 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
13239 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
13240 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
13242 #define TIM_SMCR_ETPS_Pos (12U)
13243 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
13244 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
13245 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
13246 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
13248 #define TIM_SMCR_ECE_Pos (14U)
13249 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
13250 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
13251 #define TIM_SMCR_ETP_Pos (15U)
13252 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
13253 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
13255 /******************* Bit definition for TIM_DIER register *******************/
13256 #define TIM_DIER_UIE_Pos (0U)
13257 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
13258 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
13259 #define TIM_DIER_CC1IE_Pos (1U)
13260 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
13261 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
13262 #define TIM_DIER_CC2IE_Pos (2U)
13263 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
13264 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
13265 #define TIM_DIER_CC3IE_Pos (3U)
13266 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
13267 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
13268 #define TIM_DIER_CC4IE_Pos (4U)
13269 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
13270 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
13271 #define TIM_DIER_COMIE_Pos (5U)
13272 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
13273 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
13274 #define TIM_DIER_TIE_Pos (6U)
13275 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
13276 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
13277 #define TIM_DIER_BIE_Pos (7U)
13278 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
13279 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
13280 #define TIM_DIER_UDE_Pos (8U)
13281 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
13282 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
13283 #define TIM_DIER_CC1DE_Pos (9U)
13284 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
13285 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
13286 #define TIM_DIER_CC2DE_Pos (10U)
13287 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
13288 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
13289 #define TIM_DIER_CC3DE_Pos (11U)
13290 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
13291 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
13292 #define TIM_DIER_CC4DE_Pos (12U)
13293 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
13294 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
13295 #define TIM_DIER_COMDE_Pos (13U)
13296 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
13297 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
13298 #define TIM_DIER_TDE_Pos (14U)
13299 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
13300 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
13302 /******************** Bit definition for TIM_SR register ********************/
13303 #define TIM_SR_UIF_Pos (0U)
13304 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
13305 #define TIM_SR_UIF TIM_SR_UIF_Msk
13306 #define TIM_SR_CC1IF_Pos (1U)
13307 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
13308 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
13309 #define TIM_SR_CC2IF_Pos (2U)
13310 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
13311 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
13312 #define TIM_SR_CC3IF_Pos (3U)
13313 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
13314 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
13315 #define TIM_SR_CC4IF_Pos (4U)
13316 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
13317 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
13318 #define TIM_SR_COMIF_Pos (5U)
13319 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
13320 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
13321 #define TIM_SR_TIF_Pos (6U)
13322 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
13323 #define TIM_SR_TIF TIM_SR_TIF_Msk
13324 #define TIM_SR_BIF_Pos (7U)
13325 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
13326 #define TIM_SR_BIF TIM_SR_BIF_Msk
13327 #define TIM_SR_CC1OF_Pos (9U)
13328 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
13329 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
13330 #define TIM_SR_CC2OF_Pos (10U)
13331 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
13332 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
13333 #define TIM_SR_CC3OF_Pos (11U)
13334 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
13335 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
13336 #define TIM_SR_CC4OF_Pos (12U)
13337 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
13338 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
13340 /******************* Bit definition for TIM_EGR register ********************/
13341 #define TIM_EGR_UG_Pos (0U)
13342 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
13343 #define TIM_EGR_UG TIM_EGR_UG_Msk
13344 #define TIM_EGR_CC1G_Pos (1U)
13345 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
13346 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
13347 #define TIM_EGR_CC2G_Pos (2U)
13348 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
13349 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
13350 #define TIM_EGR_CC3G_Pos (3U)
13351 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
13352 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
13353 #define TIM_EGR_CC4G_Pos (4U)
13354 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
13355 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
13356 #define TIM_EGR_COMG_Pos (5U)
13357 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
13358 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
13359 #define TIM_EGR_TG_Pos (6U)
13360 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
13361 #define TIM_EGR_TG TIM_EGR_TG_Msk
13362 #define TIM_EGR_BG_Pos (7U)
13363 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
13364 #define TIM_EGR_BG TIM_EGR_BG_Msk
13366 /****************** Bit definition for TIM_CCMR1 register *******************/
13367 #define TIM_CCMR1_CC1S_Pos (0U)
13368 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
13369 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
13370 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
13371 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
13373 #define TIM_CCMR1_OC1FE_Pos (2U)
13374 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
13375 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
13376 #define TIM_CCMR1_OC1PE_Pos (3U)
13377 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
13378 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
13380 #define TIM_CCMR1_OC1M_Pos (4U)
13381 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
13382 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
13383 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
13384 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
13385 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
13387 #define TIM_CCMR1_OC1CE_Pos (7U)
13388 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
13389 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
13391 #define TIM_CCMR1_CC2S_Pos (8U)
13392 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
13393 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
13394 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
13395 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
13397 #define TIM_CCMR1_OC2FE_Pos (10U)
13398 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
13399 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
13400 #define TIM_CCMR1_OC2PE_Pos (11U)
13401 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
13402 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
13404 #define TIM_CCMR1_OC2M_Pos (12U)
13405 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
13406 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
13407 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
13408 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
13409 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
13411 #define TIM_CCMR1_OC2CE_Pos (15U)
13412 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
13413 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
13415 /*----------------------------------------------------------------------------*/
13416 
13417 #define TIM_CCMR1_IC1PSC_Pos (2U)
13418 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
13419 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
13420 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
13421 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
13423 #define TIM_CCMR1_IC1F_Pos (4U)
13424 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
13425 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
13426 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
13427 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
13428 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
13429 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
13431 #define TIM_CCMR1_IC2PSC_Pos (10U)
13432 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
13433 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
13434 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
13435 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
13437 #define TIM_CCMR1_IC2F_Pos (12U)
13438 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
13439 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
13440 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
13441 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
13442 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
13443 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
13445 /****************** Bit definition for TIM_CCMR2 register *******************/
13446 #define TIM_CCMR2_CC3S_Pos (0U)
13447 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
13448 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
13449 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
13450 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
13452 #define TIM_CCMR2_OC3FE_Pos (2U)
13453 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
13454 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
13455 #define TIM_CCMR2_OC3PE_Pos (3U)
13456 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
13457 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
13459 #define TIM_CCMR2_OC3M_Pos (4U)
13460 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
13461 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
13462 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
13463 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
13464 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
13466 #define TIM_CCMR2_OC3CE_Pos (7U)
13467 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
13468 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
13470 #define TIM_CCMR2_CC4S_Pos (8U)
13471 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
13472 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
13473 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
13474 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
13476 #define TIM_CCMR2_OC4FE_Pos (10U)
13477 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
13478 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
13479 #define TIM_CCMR2_OC4PE_Pos (11U)
13480 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
13481 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
13483 #define TIM_CCMR2_OC4M_Pos (12U)
13484 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
13485 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
13486 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
13487 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
13488 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
13490 #define TIM_CCMR2_OC4CE_Pos (15U)
13491 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
13492 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
13494 /*----------------------------------------------------------------------------*/
13495 
13496 #define TIM_CCMR2_IC3PSC_Pos (2U)
13497 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
13498 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
13499 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
13500 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
13502 #define TIM_CCMR2_IC3F_Pos (4U)
13503 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
13504 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
13505 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
13506 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
13507 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
13508 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
13510 #define TIM_CCMR2_IC4PSC_Pos (10U)
13511 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
13512 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
13513 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
13514 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
13516 #define TIM_CCMR2_IC4F_Pos (12U)
13517 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
13518 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
13519 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
13520 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
13521 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
13522 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
13524 /******************* Bit definition for TIM_CCER register *******************/
13525 #define TIM_CCER_CC1E_Pos (0U)
13526 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
13527 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
13528 #define TIM_CCER_CC1P_Pos (1U)
13529 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
13530 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
13531 #define TIM_CCER_CC1NE_Pos (2U)
13532 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
13533 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
13534 #define TIM_CCER_CC1NP_Pos (3U)
13535 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
13536 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
13537 #define TIM_CCER_CC2E_Pos (4U)
13538 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
13539 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
13540 #define TIM_CCER_CC2P_Pos (5U)
13541 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
13542 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
13543 #define TIM_CCER_CC2NE_Pos (6U)
13544 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
13545 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
13546 #define TIM_CCER_CC2NP_Pos (7U)
13547 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
13548 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
13549 #define TIM_CCER_CC3E_Pos (8U)
13550 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
13551 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
13552 #define TIM_CCER_CC3P_Pos (9U)
13553 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
13554 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
13555 #define TIM_CCER_CC3NE_Pos (10U)
13556 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
13557 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
13558 #define TIM_CCER_CC3NP_Pos (11U)
13559 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
13560 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
13561 #define TIM_CCER_CC4E_Pos (12U)
13562 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
13563 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
13564 #define TIM_CCER_CC4P_Pos (13U)
13565 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
13566 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
13567 #define TIM_CCER_CC4NP_Pos (15U)
13568 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
13569 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
13571 /******************* Bit definition for TIM_CNT register ********************/
13572 #define TIM_CNT_CNT_Pos (0U)
13573 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
13574 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
13576 /******************* Bit definition for TIM_PSC register ********************/
13577 #define TIM_PSC_PSC_Pos (0U)
13578 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
13579 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
13581 /******************* Bit definition for TIM_ARR register ********************/
13582 #define TIM_ARR_ARR_Pos (0U)
13583 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
13584 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
13586 /******************* Bit definition for TIM_RCR register ********************/
13587 #define TIM_RCR_REP_Pos (0U)
13588 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
13589 #define TIM_RCR_REP TIM_RCR_REP_Msk
13591 /******************* Bit definition for TIM_CCR1 register *******************/
13592 #define TIM_CCR1_CCR1_Pos (0U)
13593 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
13594 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
13596 /******************* Bit definition for TIM_CCR2 register *******************/
13597 #define TIM_CCR2_CCR2_Pos (0U)
13598 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
13599 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
13601 /******************* Bit definition for TIM_CCR3 register *******************/
13602 #define TIM_CCR3_CCR3_Pos (0U)
13603 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
13604 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
13606 /******************* Bit definition for TIM_CCR4 register *******************/
13607 #define TIM_CCR4_CCR4_Pos (0U)
13608 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
13609 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
13611 /******************* Bit definition for TIM_BDTR register *******************/
13612 #define TIM_BDTR_DTG_Pos (0U)
13613 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
13614 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
13615 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
13616 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
13617 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
13618 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
13619 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
13620 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
13621 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
13622 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
13624 #define TIM_BDTR_LOCK_Pos (8U)
13625 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
13626 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
13627 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
13628 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
13630 #define TIM_BDTR_OSSI_Pos (10U)
13631 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
13632 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
13633 #define TIM_BDTR_OSSR_Pos (11U)
13634 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
13635 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
13636 #define TIM_BDTR_BKE_Pos (12U)
13637 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
13638 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
13639 #define TIM_BDTR_BKP_Pos (13U)
13640 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
13641 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
13642 #define TIM_BDTR_AOE_Pos (14U)
13643 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
13644 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
13645 #define TIM_BDTR_MOE_Pos (15U)
13646 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
13647 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
13649 /******************* Bit definition for TIM_DCR register ********************/
13650 #define TIM_DCR_DBA_Pos (0U)
13651 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
13652 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
13653 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
13654 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
13655 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
13656 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
13657 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
13659 #define TIM_DCR_DBL_Pos (8U)
13660 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
13661 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
13662 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
13663 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
13664 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
13665 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
13666 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
13668 /******************* Bit definition for TIM_DMAR register *******************/
13669 #define TIM_DMAR_DMAB_Pos (0U)
13670 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
13671 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
13673 /******************* Bit definition for TIM_OR register *********************/
13674 #define TIM_OR_TI1_RMP_Pos (0U)
13675 #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
13676 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
13677 #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
13678 #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
13680 #define TIM_OR_TI4_RMP_Pos (6U)
13681 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
13682 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
13683 #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
13684 #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
13685 #define TIM_OR_ITR1_RMP_Pos (10U)
13686 #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
13687 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
13688 #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
13689 #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
13692 /******************************************************************************/
13693 /* */
13694 /* Universal Synchronous Asynchronous Receiver Transmitter */
13695 /* */
13696 /******************************************************************************/
13697 /******************* Bit definition for USART_SR register *******************/
13698 #define USART_SR_PE_Pos (0U)
13699 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
13700 #define USART_SR_PE USART_SR_PE_Msk
13701 #define USART_SR_FE_Pos (1U)
13702 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
13703 #define USART_SR_FE USART_SR_FE_Msk
13704 #define USART_SR_NE_Pos (2U)
13705 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
13706 #define USART_SR_NE USART_SR_NE_Msk
13707 #define USART_SR_ORE_Pos (3U)
13708 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
13709 #define USART_SR_ORE USART_SR_ORE_Msk
13710 #define USART_SR_IDLE_Pos (4U)
13711 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
13712 #define USART_SR_IDLE USART_SR_IDLE_Msk
13713 #define USART_SR_RXNE_Pos (5U)
13714 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
13715 #define USART_SR_RXNE USART_SR_RXNE_Msk
13716 #define USART_SR_TC_Pos (6U)
13717 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
13718 #define USART_SR_TC USART_SR_TC_Msk
13719 #define USART_SR_TXE_Pos (7U)
13720 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
13721 #define USART_SR_TXE USART_SR_TXE_Msk
13722 #define USART_SR_LBD_Pos (8U)
13723 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
13724 #define USART_SR_LBD USART_SR_LBD_Msk
13725 #define USART_SR_CTS_Pos (9U)
13726 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
13727 #define USART_SR_CTS USART_SR_CTS_Msk
13729 /******************* Bit definition for USART_DR register *******************/
13730 #define USART_DR_DR_Pos (0U)
13731 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
13732 #define USART_DR_DR USART_DR_DR_Msk
13734 /****************** Bit definition for USART_BRR register *******************/
13735 #define USART_BRR_DIV_Fraction_Pos (0U)
13736 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
13737 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
13738 #define USART_BRR_DIV_Mantissa_Pos (4U)
13739 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
13740 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
13742 /****************** Bit definition for USART_CR1 register *******************/
13743 #define USART_CR1_SBK_Pos (0U)
13744 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
13745 #define USART_CR1_SBK USART_CR1_SBK_Msk
13746 #define USART_CR1_RWU_Pos (1U)
13747 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
13748 #define USART_CR1_RWU USART_CR1_RWU_Msk
13749 #define USART_CR1_RE_Pos (2U)
13750 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
13751 #define USART_CR1_RE USART_CR1_RE_Msk
13752 #define USART_CR1_TE_Pos (3U)
13753 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
13754 #define USART_CR1_TE USART_CR1_TE_Msk
13755 #define USART_CR1_IDLEIE_Pos (4U)
13756 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
13757 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
13758 #define USART_CR1_RXNEIE_Pos (5U)
13759 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
13760 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
13761 #define USART_CR1_TCIE_Pos (6U)
13762 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
13763 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
13764 #define USART_CR1_TXEIE_Pos (7U)
13765 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
13766 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
13767 #define USART_CR1_PEIE_Pos (8U)
13768 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
13769 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
13770 #define USART_CR1_PS_Pos (9U)
13771 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
13772 #define USART_CR1_PS USART_CR1_PS_Msk
13773 #define USART_CR1_PCE_Pos (10U)
13774 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
13775 #define USART_CR1_PCE USART_CR1_PCE_Msk
13776 #define USART_CR1_WAKE_Pos (11U)
13777 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
13778 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
13779 #define USART_CR1_M_Pos (12U)
13780 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
13781 #define USART_CR1_M USART_CR1_M_Msk
13782 #define USART_CR1_UE_Pos (13U)
13783 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
13784 #define USART_CR1_UE USART_CR1_UE_Msk
13785 #define USART_CR1_OVER8_Pos (15U)
13786 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
13787 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
13789 /****************** Bit definition for USART_CR2 register *******************/
13790 #define USART_CR2_ADD_Pos (0U)
13791 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
13792 #define USART_CR2_ADD USART_CR2_ADD_Msk
13793 #define USART_CR2_LBDL_Pos (5U)
13794 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
13795 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
13796 #define USART_CR2_LBDIE_Pos (6U)
13797 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
13798 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
13799 #define USART_CR2_LBCL_Pos (8U)
13800 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
13801 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
13802 #define USART_CR2_CPHA_Pos (9U)
13803 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
13804 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
13805 #define USART_CR2_CPOL_Pos (10U)
13806 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
13807 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
13808 #define USART_CR2_CLKEN_Pos (11U)
13809 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
13810 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
13812 #define USART_CR2_STOP_Pos (12U)
13813 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
13814 #define USART_CR2_STOP USART_CR2_STOP_Msk
13815 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
13816 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
13818 #define USART_CR2_LINEN_Pos (14U)
13819 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
13820 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
13822 /****************** Bit definition for USART_CR3 register *******************/
13823 #define USART_CR3_EIE_Pos (0U)
13824 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
13825 #define USART_CR3_EIE USART_CR3_EIE_Msk
13826 #define USART_CR3_IREN_Pos (1U)
13827 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
13828 #define USART_CR3_IREN USART_CR3_IREN_Msk
13829 #define USART_CR3_IRLP_Pos (2U)
13830 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
13831 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
13832 #define USART_CR3_HDSEL_Pos (3U)
13833 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
13834 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
13835 #define USART_CR3_NACK_Pos (4U)
13836 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
13837 #define USART_CR3_NACK USART_CR3_NACK_Msk
13838 #define USART_CR3_SCEN_Pos (5U)
13839 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
13840 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
13841 #define USART_CR3_DMAR_Pos (6U)
13842 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
13843 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
13844 #define USART_CR3_DMAT_Pos (7U)
13845 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
13846 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
13847 #define USART_CR3_RTSE_Pos (8U)
13848 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
13849 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
13850 #define USART_CR3_CTSE_Pos (9U)
13851 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
13852 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
13853 #define USART_CR3_CTSIE_Pos (10U)
13854 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
13855 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
13856 #define USART_CR3_ONEBIT_Pos (11U)
13857 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
13858 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
13860 /****************** Bit definition for USART_GTPR register ******************/
13861 #define USART_GTPR_PSC_Pos (0U)
13862 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
13863 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
13864 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
13865 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
13866 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
13867 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
13868 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
13869 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
13870 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
13871 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
13873 #define USART_GTPR_GT_Pos (8U)
13874 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
13875 #define USART_GTPR_GT USART_GTPR_GT_Msk
13877 /******************************************************************************/
13878 /* */
13879 /* Window WATCHDOG */
13880 /* */
13881 /******************************************************************************/
13882 /******************* Bit definition for WWDG_CR register ********************/
13883 #define WWDG_CR_T_Pos (0U)
13884 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
13885 #define WWDG_CR_T WWDG_CR_T_Msk
13886 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
13887 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
13888 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
13889 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
13890 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
13891 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
13892 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
13893 /* Legacy defines */
13894 #define WWDG_CR_T0 WWDG_CR_T_0
13895 #define WWDG_CR_T1 WWDG_CR_T_1
13896 #define WWDG_CR_T2 WWDG_CR_T_2
13897 #define WWDG_CR_T3 WWDG_CR_T_3
13898 #define WWDG_CR_T4 WWDG_CR_T_4
13899 #define WWDG_CR_T5 WWDG_CR_T_5
13900 #define WWDG_CR_T6 WWDG_CR_T_6
13901 
13902 #define WWDG_CR_WDGA_Pos (7U)
13903 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
13904 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
13906 /******************* Bit definition for WWDG_CFR register *******************/
13907 #define WWDG_CFR_W_Pos (0U)
13908 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
13909 #define WWDG_CFR_W WWDG_CFR_W_Msk
13910 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
13911 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
13912 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
13913 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
13914 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
13915 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
13916 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
13917 /* Legacy defines */
13918 #define WWDG_CFR_W0 WWDG_CFR_W_0
13919 #define WWDG_CFR_W1 WWDG_CFR_W_1
13920 #define WWDG_CFR_W2 WWDG_CFR_W_2
13921 #define WWDG_CFR_W3 WWDG_CFR_W_3
13922 #define WWDG_CFR_W4 WWDG_CFR_W_4
13923 #define WWDG_CFR_W5 WWDG_CFR_W_5
13924 #define WWDG_CFR_W6 WWDG_CFR_W_6
13925 
13926 #define WWDG_CFR_WDGTB_Pos (7U)
13927 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
13928 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
13929 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
13930 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
13931 /* Legacy defines */
13932 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
13933 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
13934 
13935 #define WWDG_CFR_EWI_Pos (9U)
13936 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
13937 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
13939 /******************* Bit definition for WWDG_SR register ********************/
13940 #define WWDG_SR_EWIF_Pos (0U)
13941 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
13942 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
13945 /******************************************************************************/
13946 /* */
13947 /* DBG */
13948 /* */
13949 /******************************************************************************/
13950 /******************** Bit definition for DBGMCU_IDCODE register *************/
13951 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
13952 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
13953 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
13954 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
13955 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
13956 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
13957 
13958 /******************** Bit definition for DBGMCU_CR register *****************/
13959 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
13960 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
13961 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
13962 #define DBGMCU_CR_DBG_STOP_Pos (1U)
13963 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
13964 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
13965 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
13966 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
13967 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
13968 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
13969 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
13970 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
13971 
13972 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
13973 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
13974 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
13975 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
13976 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
13978 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
13979 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
13980 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
13981 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13982 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
13983 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
13984 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13985 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
13986 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
13987 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13988 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
13989 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
13990 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13991 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
13992 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
13993 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13994 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
13995 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
13996 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13997 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
13998 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
13999 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14000 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14001 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
14002 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14003 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14004 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
14005 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14006 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14007 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
14008 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14009 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14010 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
14011 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14012 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14013 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
14014 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14015 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14016 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
14017 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14018 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14019 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
14020 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14021 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14022 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
14023 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14024 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
14025 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
14026 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
14027 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14028 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
14029 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14030 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14031 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
14032 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14033 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
14034 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
14035 
14036 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
14037 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14038 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
14039 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14040 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14041 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
14042 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14043 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14044 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
14045 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14046 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14047 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
14048 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14049 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14050 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
14051 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14052 
14053 /******************************************************************************/
14054 /* */
14055 /* USB_OTG */
14056 /* */
14057 /******************************************************************************/
14058 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
14059 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
14060 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
14061 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
14062 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
14063 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
14064 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
14065 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
14066 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
14067 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
14068 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
14069 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
14070 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
14071 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
14072 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
14073 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
14074 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
14075 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
14076 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
14077 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
14078 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
14079 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
14080 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
14081 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
14082 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
14083 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
14084 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
14085 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
14086 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
14087 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
14088 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
14089 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
14090 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
14091 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
14092 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
14093 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
14094 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
14095 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
14096 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
14097 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
14098 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
14099 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
14100 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
14101 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
14102 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
14103 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
14104 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
14105 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
14106 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
14107 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
14108 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
14109 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
14110 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
14111 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
14112 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
14114 /******************** Bit definition forUSB_OTG_HCFG register ********************/
14115 
14116 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
14117 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
14118 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
14119 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
14120 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
14121 #define USB_OTG_HCFG_FSLSS_Pos (2U)
14122 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
14123 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
14125 /******************** Bit definition for USB_OTG_DCFG register ********************/
14126 
14127 #define USB_OTG_DCFG_DSPD_Pos (0U)
14128 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
14129 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
14130 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
14131 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
14132 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
14133 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
14134 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
14136 #define USB_OTG_DCFG_DAD_Pos (4U)
14137 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
14138 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
14139 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
14140 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
14141 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
14142 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
14143 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
14144 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
14145 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
14147 #define USB_OTG_DCFG_PFIVL_Pos (11U)
14148 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
14149 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
14150 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
14151 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
14153 #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
14154 #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
14155 #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
14157 #define USB_OTG_DCFG_ERRATIM_Pos (15U)
14158 #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
14159 #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
14161 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
14162 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
14163 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
14164 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
14165 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
14167 /******************** Bit definition for USB_OTG_PCGCR register ********************/
14168 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
14169 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
14170 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
14171 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
14172 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
14173 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
14174 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
14175 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
14176 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
14178 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
14179 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
14180 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
14181 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
14182 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
14183 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
14184 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
14185 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
14186 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
14187 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
14188 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
14189 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
14190 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
14191 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
14192 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
14193 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
14194 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
14195 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
14196 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
14197 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
14198 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
14199 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
14201 /******************** Bit definition for USB_OTG_DCTL register ********************/
14202 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
14203 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
14204 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
14205 #define USB_OTG_DCTL_SDIS_Pos (1U)
14206 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
14207 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
14208 #define USB_OTG_DCTL_GINSTS_Pos (2U)
14209 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
14210 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
14211 #define USB_OTG_DCTL_GONSTS_Pos (3U)
14212 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
14213 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
14215 #define USB_OTG_DCTL_TCTL_Pos (4U)
14216 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
14217 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
14218 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
14219 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
14220 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
14221 #define USB_OTG_DCTL_SGINAK_Pos (7U)
14222 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
14223 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
14224 #define USB_OTG_DCTL_CGINAK_Pos (8U)
14225 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
14226 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
14227 #define USB_OTG_DCTL_SGONAK_Pos (9U)
14228 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
14229 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
14230 #define USB_OTG_DCTL_CGONAK_Pos (10U)
14231 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
14232 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
14233 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
14234 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
14235 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
14237 /******************** Bit definition for USB_OTG_HFIR register ********************/
14238 #define USB_OTG_HFIR_FRIVL_Pos (0U)
14239 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
14240 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
14242 /******************** Bit definition for USB_OTG_HFNUM register ********************/
14243 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
14244 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
14245 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
14246 #define USB_OTG_HFNUM_FTREM_Pos (16U)
14247 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
14248 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
14250 /******************** Bit definition for USB_OTG_DSTS register ********************/
14251 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
14252 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
14253 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
14255 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
14256 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
14257 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
14258 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
14259 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
14260 #define USB_OTG_DSTS_EERR_Pos (3U)
14261 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
14262 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
14263 #define USB_OTG_DSTS_FNSOF_Pos (8U)
14264 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
14265 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
14267 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
14268 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
14269 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
14270 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
14271 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
14272 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
14273 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
14274 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
14275 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
14276 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
14277 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
14278 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
14279 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
14280 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
14281 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
14282 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
14283 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
14284 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
14285 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
14286 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
14287 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
14289 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
14290 
14291 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
14292 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
14293 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
14294 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
14295 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
14296 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
14297 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
14298 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
14299 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
14300 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
14301 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
14302 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
14303 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
14304 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
14305 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
14306 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
14307 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
14308 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
14309 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
14310 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
14311 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
14312 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
14313 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
14314 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
14315 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
14316 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
14317 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
14318 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
14319 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
14320 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
14321 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
14322 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
14323 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
14324 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
14325 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
14326 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
14327 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
14328 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
14329 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
14330 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
14331 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
14332 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
14333 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
14334 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
14335 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
14336 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
14337 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
14338 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
14339 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
14340 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
14341 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
14342 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
14343 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
14344 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
14345 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
14346 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
14347 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
14348 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
14349 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
14350 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
14351 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
14353 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
14354 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
14355 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
14356 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
14357 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
14358 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
14359 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
14360 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
14361 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
14362 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
14363 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
14364 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
14365 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
14366 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
14367 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
14368 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
14371 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
14372 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14373 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
14374 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14375 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14376 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14377 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14378 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14379 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
14380 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
14381 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
14382 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
14383 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
14384 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
14386 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
14387 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
14388 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
14389 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
14390 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
14391 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
14392 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
14393 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
14394 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
14395 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
14396 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
14397 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
14398 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
14399 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
14400 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
14401 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
14402 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
14403 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
14404 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
14405 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
14406 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
14407 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
14408 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
14409 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
14410 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
14412 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
14413 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
14414 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
14415 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
14416 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
14417 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14418 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
14419 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14420 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14421 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14422 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14423 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14424 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14425 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14426 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14428 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
14429 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14430 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
14431 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14432 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14433 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14434 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14435 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14436 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14437 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14438 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14440 /******************** Bit definition for USB_OTG_HAINT register ********************/
14441 #define USB_OTG_HAINT_HAINT_Pos (0U)
14442 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
14443 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
14445 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
14446 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
14447 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
14448 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
14449 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
14450 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
14451 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
14452 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
14453 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
14454 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
14455 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
14456 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
14457 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
14458 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
14459 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
14460 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
14461 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
14462 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
14463 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
14464 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
14465 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
14466 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
14467 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
14468 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
14469 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
14470 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
14471 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
14472 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
14473 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
14474 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
14475 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
14476 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
14477 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
14478 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
14479 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
14480 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
14481 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
14482 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
14483 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
14484 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
14485 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
14486 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
14487 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
14488 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
14489 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
14490 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
14491 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
14492 #define USB_OTG_GINTSTS_SOF_Pos (3U)
14493 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
14494 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
14495 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
14496 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
14497 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
14498 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
14499 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
14500 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
14501 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
14502 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
14503 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
14504 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
14505 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
14506 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
14507 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
14508 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
14509 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
14510 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
14511 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
14512 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
14513 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
14514 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
14515 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
14516 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
14517 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
14518 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
14519 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
14520 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
14521 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
14522 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
14523 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
14524 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
14525 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
14526 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
14527 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
14528 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
14529 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
14530 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
14531 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
14532 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
14533 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
14534 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
14535 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
14536 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
14537 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
14538 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
14539 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
14540 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
14541 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
14542 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
14543 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14544 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
14545 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
14546 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
14547 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
14548 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
14549 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14550 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
14551 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
14552 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
14553 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
14554 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
14555 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14556 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
14557 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
14558 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14559 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
14560 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14561 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14562 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14563 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14564 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14565 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14566 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14568 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
14569 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
14570 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14571 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14572 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14573 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14574 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14575 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
14576 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14577 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14578 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14579 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14580 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14581 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14582 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14583 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14584 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14585 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14586 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14587 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14588 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14589 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14590 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14591 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14592 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14593 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14594 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14595 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14596 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
14597 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14598 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14599 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14600 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14601 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14602 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14603 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14604 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14605 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14606 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14607 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14608 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14609 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14610 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14611 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14612 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14613 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14614 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14615 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14616 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14617 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14618 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14619 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14620 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14621 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14622 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14623 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14624 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14625 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14626 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
14627 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
14628 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
14629 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14630 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14631 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14632 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
14633 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14634 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14635 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14636 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14637 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14638 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
14639 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
14640 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
14641 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14642 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14643 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14644 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14645 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14646 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14647 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14648 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14649 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14650 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
14651 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14652 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14654 /******************** Bit definition for USB_OTG_DAINT register ********************/
14655 #define USB_OTG_DAINT_IEPINT_Pos (0U)
14656 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14657 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14658 #define USB_OTG_DAINT_OEPINT_Pos (16U)
14659 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14660 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14662 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14663 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14664 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14665 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14667 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14668 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14669 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14670 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14671 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14672 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14673 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14674 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
14675 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14676 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14677 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14678 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14679 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14681 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14682 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14683 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14684 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14685 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14686 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14687 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14689 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14690 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14691 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14692 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14694 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14695 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14696 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14697 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14699 /******************** Bit definition for OTG register ********************/
14700 #define USB_OTG_NPTXFSA_Pos (0U)
14701 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14702 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14703 #define USB_OTG_NPTXFD_Pos (16U)
14704 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14705 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14706 #define USB_OTG_TX0FSA_Pos (0U)
14707 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14708 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14709 #define USB_OTG_TX0FD_Pos (16U)
14710 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14711 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14713 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14714 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14715 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14716 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14718 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14719 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14720 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14721 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14723 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14724 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14725 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14726 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14727 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14728 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14729 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14730 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14731 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14732 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14733 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14735 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14736 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14737 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14738 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14739 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14740 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14741 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14742 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14743 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14744 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14746 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14747 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14748 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14749 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14750 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14751 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14752 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14754 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14755 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14756 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14757 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14758 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14759 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14760 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14761 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14762 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14763 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14764 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14765 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14766 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14767 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14768 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14770 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14771 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14772 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14773 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14774 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14775 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14776 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14777 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14778 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14779 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14780 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14781 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14782 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14783 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14784 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14786 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14787 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14788 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14789 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14791 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
14792 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14793 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14794 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14795 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14796 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14797 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14799 /******************** Bit definition for USB_OTG_GCCFG register ********************/
14800 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14801 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14802 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14803 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
14804 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
14805 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
14807 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14808 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14809 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14810 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14811 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14812 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14813 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14815 /******************** Bit definition for USB_OTG_CID register ********************/
14816 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14817 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14818 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14820 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
14821 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
14822 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
14823 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
14824 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
14825 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
14826 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
14827 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
14828 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
14829 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
14830 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
14831 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
14832 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
14833 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
14834 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
14835 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
14836 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
14837 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
14838 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
14839 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
14840 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
14841 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
14842 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
14843 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
14844 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
14845 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
14846 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
14847 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
14848 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
14849 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
14850 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
14851 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
14852 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
14853 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
14854 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
14855 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
14856 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
14857 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
14858 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
14859 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
14860 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
14861 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
14862 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
14863 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
14864 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
14865 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
14867 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14868 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14869 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14870 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14871 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14872 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14873 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14874 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14875 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14876 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14877 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14878 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14879 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14880 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14881 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14882 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14883 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14884 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14885 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14886 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14887 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14888 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14889 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14890 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14891 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14892 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14893 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14894 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14896 /******************** Bit definition for USB_OTG_HPRT register ********************/
14897 #define USB_OTG_HPRT_PCSTS_Pos (0U)
14898 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14899 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14900 #define USB_OTG_HPRT_PCDET_Pos (1U)
14901 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14902 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14903 #define USB_OTG_HPRT_PENA_Pos (2U)
14904 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14905 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14906 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
14907 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14908 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14909 #define USB_OTG_HPRT_POCA_Pos (4U)
14910 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14911 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14912 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
14913 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14914 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14915 #define USB_OTG_HPRT_PRES_Pos (6U)
14916 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14917 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14918 #define USB_OTG_HPRT_PSUSP_Pos (7U)
14919 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14920 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14921 #define USB_OTG_HPRT_PRST_Pos (8U)
14922 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14923 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14925 #define USB_OTG_HPRT_PLSTS_Pos (10U)
14926 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14927 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14928 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14929 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14930 #define USB_OTG_HPRT_PPWR_Pos (12U)
14931 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14932 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14934 #define USB_OTG_HPRT_PTCTL_Pos (13U)
14935 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14936 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14937 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14938 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14939 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14940 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14942 #define USB_OTG_HPRT_PSPD_Pos (17U)
14943 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14944 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14945 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14946 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14948 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14949 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14950 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14951 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14952 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14953 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14954 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14955 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14956 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14957 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14958 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14959 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14960 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14961 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14962 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14963 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14964 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14965 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14966 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14967 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14968 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14969 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14970 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14971 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14972 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14973 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14974 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14975 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14976 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14977 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14978 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14979 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14980 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14981 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14983 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14984 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14985 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14986 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14987 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14988 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14989 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14991 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14992 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14993 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14994 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14995 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14996 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14997 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14998 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14999 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
15000 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
15001 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
15002 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
15003 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
15005 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
15006 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
15007 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
15008 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
15009 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
15010 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
15011 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
15012 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
15014 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
15015 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
15016 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
15017 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
15018 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
15019 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
15020 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
15021 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
15022 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
15023 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
15024 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
15025 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
15026 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
15027 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
15028 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
15029 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
15030 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
15031 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
15032 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
15033 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
15034 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
15035 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
15036 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
15037 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
15038 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
15040 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
15041 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
15042 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
15043 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
15045 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
15046 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
15047 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
15048 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
15049 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
15050 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
15051 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
15052 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
15053 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
15054 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
15055 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
15056 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
15057 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
15059 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
15060 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
15061 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
15062 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
15063 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
15065 #define USB_OTG_HCCHAR_MC_Pos (20U)
15066 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
15067 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
15068 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
15069 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
15071 #define USB_OTG_HCCHAR_DAD_Pos (22U)
15072 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
15073 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
15074 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
15075 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
15076 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
15077 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
15078 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
15079 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
15080 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
15081 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
15082 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
15083 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
15084 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
15085 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
15086 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
15087 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
15088 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
15089 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
15091 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
15092 
15093 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
15094 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
15095 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
15096 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15097 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15098 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15099 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15100 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15101 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15102 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
15104 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
15105 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
15106 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
15107 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15108 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15109 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15110 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15111 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15112 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15113 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
15115 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
15116 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
15117 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
15118 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
15119 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
15120 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
15121 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
15122 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
15123 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
15124 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
15125 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
15127 /******************** Bit definition for USB_OTG_HCINT register ********************/
15128 #define USB_OTG_HCINT_XFRC_Pos (0U)
15129 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
15130 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
15131 #define USB_OTG_HCINT_CHH_Pos (1U)
15132 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
15133 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
15134 #define USB_OTG_HCINT_AHBERR_Pos (2U)
15135 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
15136 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
15137 #define USB_OTG_HCINT_STALL_Pos (3U)
15138 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
15139 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
15140 #define USB_OTG_HCINT_NAK_Pos (4U)
15141 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
15142 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
15143 #define USB_OTG_HCINT_ACK_Pos (5U)
15144 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
15145 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
15146 #define USB_OTG_HCINT_NYET_Pos (6U)
15147 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
15148 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
15149 #define USB_OTG_HCINT_TXERR_Pos (7U)
15150 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
15151 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
15152 #define USB_OTG_HCINT_BBERR_Pos (8U)
15153 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
15154 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
15155 #define USB_OTG_HCINT_FRMOR_Pos (9U)
15156 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
15157 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
15158 #define USB_OTG_HCINT_DTERR_Pos (10U)
15159 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
15160 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
15162 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
15163 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
15164 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
15165 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
15166 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
15167 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
15168 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
15169 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
15170 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
15171 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
15172 #define USB_OTG_DIEPINT_TOC_Pos (3U)
15173 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
15174 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
15175 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
15176 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
15177 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
15178 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
15179 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
15180 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
15181 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
15182 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
15183 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
15184 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
15185 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
15186 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
15187 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
15188 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
15189 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
15190 #define USB_OTG_DIEPINT_BNA_Pos (9U)
15191 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
15192 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
15193 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
15194 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
15195 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
15196 #define USB_OTG_DIEPINT_BERR_Pos (12U)
15197 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
15198 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
15199 #define USB_OTG_DIEPINT_NAK_Pos (13U)
15200 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
15201 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
15203 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
15204 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
15205 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
15206 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
15207 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
15208 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
15209 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
15210 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
15211 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
15212 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
15213 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
15214 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
15215 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
15216 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
15217 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
15218 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
15219 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
15220 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
15221 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
15222 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
15223 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
15224 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
15225 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
15226 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
15227 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
15228 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
15229 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
15230 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
15231 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
15232 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
15233 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
15234 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
15235 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
15236 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
15238 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
15239 
15240 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
15241 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
15242 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
15243 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
15244 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
15245 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
15246 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
15247 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
15248 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
15249 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
15250 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
15251 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
15252 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
15253 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
15254 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
15255 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
15256 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
15257 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
15258 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
15259 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
15260 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
15261 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
15262 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
15263 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
15265 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
15266 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
15267 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
15268 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
15270 /******************** Bit definition for USB_OTG_HCDMA register ********************/
15271 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
15272 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
15273 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
15275 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
15276 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
15277 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
15278 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
15280 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
15281 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
15282 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
15283 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
15284 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
15285 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
15286 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
15288 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
15289 
15290 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
15291 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
15292 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
15293 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
15294 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
15295 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
15296 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
15297 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
15298 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
15299 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
15300 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
15301 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
15302 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
15303 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
15304 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
15305 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
15306 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
15307 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
15308 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
15309 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
15310 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
15311 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
15312 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
15313 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
15314 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
15315 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
15316 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
15317 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
15318 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
15319 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
15320 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
15321 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
15322 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
15323 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
15324 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
15325 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
15326 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
15327 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
15329 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
15330 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
15331 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
15332 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
15333 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
15334 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
15335 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
15336 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
15337 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
15338 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
15339 #define USB_OTG_DOEPINT_STUP_Pos (3U)
15340 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
15341 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
15342 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
15343 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
15344 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
15345 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
15346 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
15347 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
15348 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
15349 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
15350 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
15351 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
15352 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
15353 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
15354 #define USB_OTG_DOEPINT_NAK_Pos (13U)
15355 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
15356 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
15357 #define USB_OTG_DOEPINT_NYET_Pos (14U)
15358 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
15359 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
15360 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
15361 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
15362 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
15363 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
15364 
15365 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
15366 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
15367 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
15368 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
15369 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
15370 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
15372 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
15373 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15374 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
15375 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15376 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15378 /******************** Bit definition for PCGCCTL register ********************/
15379 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
15380 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
15381 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
15382 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
15383 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
15384 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
15385 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
15386 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
15387 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
15389 /* Legacy define */
15390 /******************** Bit definition for OTG register ********************/
15391 #define USB_OTG_CHNUM_Pos (0U)
15392 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
15393 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
15394 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
15395 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
15396 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
15397 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
15398 #define USB_OTG_BCNT_Pos (4U)
15399 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
15400 #define USB_OTG_BCNT USB_OTG_BCNT_Msk
15402 #define USB_OTG_DPID_Pos (15U)
15403 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
15404 #define USB_OTG_DPID USB_OTG_DPID_Msk
15405 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
15406 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
15408 #define USB_OTG_PKTSTS_Pos (17U)
15409 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
15410 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
15411 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
15412 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
15413 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
15414 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
15416 #define USB_OTG_EPNUM_Pos (0U)
15417 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
15418 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
15419 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
15420 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
15421 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
15422 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
15424 #define USB_OTG_FRMNUM_Pos (21U)
15425 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
15426 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
15427 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
15428 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
15429 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
15430 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
15443 /******************************* ADC Instances ********************************/
15444 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15445  ((INSTANCE) == ADC2) || \
15446  ((INSTANCE) == ADC3))
15447 
15448 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15449 
15450 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
15451 
15452 /******************************* CAN Instances ********************************/
15453 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15454  ((INSTANCE) == CAN2))
15455 /******************************* CRC Instances ********************************/
15456 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15457 
15458 /******************************* DAC Instances ********************************/
15459 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15460 
15461 /******************************* DCMI Instances *******************************/
15462 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
15463 
15464 /******************************** DMA Instances *******************************/
15465 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15466  ((INSTANCE) == DMA1_Stream1) || \
15467  ((INSTANCE) == DMA1_Stream2) || \
15468  ((INSTANCE) == DMA1_Stream3) || \
15469  ((INSTANCE) == DMA1_Stream4) || \
15470  ((INSTANCE) == DMA1_Stream5) || \
15471  ((INSTANCE) == DMA1_Stream6) || \
15472  ((INSTANCE) == DMA1_Stream7) || \
15473  ((INSTANCE) == DMA2_Stream0) || \
15474  ((INSTANCE) == DMA2_Stream1) || \
15475  ((INSTANCE) == DMA2_Stream2) || \
15476  ((INSTANCE) == DMA2_Stream3) || \
15477  ((INSTANCE) == DMA2_Stream4) || \
15478  ((INSTANCE) == DMA2_Stream5) || \
15479  ((INSTANCE) == DMA2_Stream6) || \
15480  ((INSTANCE) == DMA2_Stream7))
15481 
15482 /******************************* GPIO Instances *******************************/
15483 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15484  ((INSTANCE) == GPIOB) || \
15485  ((INSTANCE) == GPIOC) || \
15486  ((INSTANCE) == GPIOD) || \
15487  ((INSTANCE) == GPIOE) || \
15488  ((INSTANCE) == GPIOF) || \
15489  ((INSTANCE) == GPIOG) || \
15490  ((INSTANCE) == GPIOH))
15491 
15492 /******************************** I2C Instances *******************************/
15493 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15494  ((INSTANCE) == I2C2) || \
15495  ((INSTANCE) == I2C3))
15496 
15497 /******************************* SMBUS Instances ******************************/
15498 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
15499 
15500 /******************************** I2S Instances *******************************/
15501 #define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
15502  ((INSTANCE) == SPI3))
15503 
15504 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15505  ((INSTANCE) == SPI2) || \
15506  ((INSTANCE) == SPI3))
15507 
15508 
15509 
15510 /****************************** RTC Instances *********************************/
15511 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15512 
15513 /******************************* SAI Instances ********************************/
15514 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
15515  ((PERIPH) == SAI1_Block_B) || \
15516  ((PERIPH) == SAI2_Block_A) || \
15517  ((PERIPH) == SAI2_Block_B))
15518 /* Legacy define */
15519 
15520 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
15521 
15522 /******************************** SPI Instances *******************************/
15523 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15524  ((INSTANCE) == SPI2) || \
15525  ((INSTANCE) == SPI3) || \
15526  ((INSTANCE) == SPI4))
15527 
15528 
15529 /****************** TIM Instances : All supported instances *******************/
15530 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15531  ((INSTANCE) == TIM2) || \
15532  ((INSTANCE) == TIM3) || \
15533  ((INSTANCE) == TIM4) || \
15534  ((INSTANCE) == TIM5) || \
15535  ((INSTANCE) == TIM6) || \
15536  ((INSTANCE) == TIM7) || \
15537  ((INSTANCE) == TIM8) || \
15538  ((INSTANCE) == TIM9) || \
15539  ((INSTANCE) == TIM10)|| \
15540  ((INSTANCE) == TIM11)|| \
15541  ((INSTANCE) == TIM12)|| \
15542  ((INSTANCE) == TIM13)|| \
15543  ((INSTANCE) == TIM14))
15544 
15545 /************* TIM Instances : at least 1 capture/compare channel *************/
15546 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15547  ((INSTANCE) == TIM2) || \
15548  ((INSTANCE) == TIM3) || \
15549  ((INSTANCE) == TIM4) || \
15550  ((INSTANCE) == TIM5) || \
15551  ((INSTANCE) == TIM8) || \
15552  ((INSTANCE) == TIM9) || \
15553  ((INSTANCE) == TIM10) || \
15554  ((INSTANCE) == TIM11) || \
15555  ((INSTANCE) == TIM12) || \
15556  ((INSTANCE) == TIM13) || \
15557  ((INSTANCE) == TIM14))
15558 
15559 /************ TIM Instances : at least 2 capture/compare channels *************/
15560 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15561  ((INSTANCE) == TIM2) || \
15562  ((INSTANCE) == TIM3) || \
15563  ((INSTANCE) == TIM4) || \
15564  ((INSTANCE) == TIM5) || \
15565  ((INSTANCE) == TIM8) || \
15566  ((INSTANCE) == TIM9) || \
15567  ((INSTANCE) == TIM12))
15568 
15569 /************ TIM Instances : at least 3 capture/compare channels *************/
15570 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15571  ((INSTANCE) == TIM2) || \
15572  ((INSTANCE) == TIM3) || \
15573  ((INSTANCE) == TIM4) || \
15574  ((INSTANCE) == TIM5) || \
15575  ((INSTANCE) == TIM8))
15576 
15577 /************ TIM Instances : at least 4 capture/compare channels *************/
15578 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15579  ((INSTANCE) == TIM2) || \
15580  ((INSTANCE) == TIM3) || \
15581  ((INSTANCE) == TIM4) || \
15582  ((INSTANCE) == TIM5) || \
15583  ((INSTANCE) == TIM8))
15584 
15585 /******************** TIM Instances : Advanced-control timers *****************/
15586 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15587  ((INSTANCE) == TIM8))
15588 
15589 /******************* TIM Instances : Timer input XOR function *****************/
15590 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15591  ((INSTANCE) == TIM2) || \
15592  ((INSTANCE) == TIM3) || \
15593  ((INSTANCE) == TIM4) || \
15594  ((INSTANCE) == TIM5) || \
15595  ((INSTANCE) == TIM8))
15596 
15597 /****************** TIM Instances : DMA requests generation (UDE) *************/
15598 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15599  ((INSTANCE) == TIM2) || \
15600  ((INSTANCE) == TIM3) || \
15601  ((INSTANCE) == TIM4) || \
15602  ((INSTANCE) == TIM5) || \
15603  ((INSTANCE) == TIM6) || \
15604  ((INSTANCE) == TIM7) || \
15605  ((INSTANCE) == TIM8))
15606 
15607 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
15608 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15609  ((INSTANCE) == TIM2) || \
15610  ((INSTANCE) == TIM3) || \
15611  ((INSTANCE) == TIM4) || \
15612  ((INSTANCE) == TIM5) || \
15613  ((INSTANCE) == TIM8))
15614 
15615 /************ TIM Instances : DMA requests generation (COMDE) *****************/
15616 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15617  ((INSTANCE) == TIM2) || \
15618  ((INSTANCE) == TIM3) || \
15619  ((INSTANCE) == TIM4) || \
15620  ((INSTANCE) == TIM5) || \
15621  ((INSTANCE) == TIM8))
15622 
15623 /******************** TIM Instances : DMA burst feature ***********************/
15624 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15625  ((INSTANCE) == TIM2) || \
15626  ((INSTANCE) == TIM3) || \
15627  ((INSTANCE) == TIM4) || \
15628  ((INSTANCE) == TIM5) || \
15629  ((INSTANCE) == TIM8))
15630 
15631 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15632 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15633  ((INSTANCE) == TIM2) || \
15634  ((INSTANCE) == TIM3) || \
15635  ((INSTANCE) == TIM4) || \
15636  ((INSTANCE) == TIM5) || \
15637  ((INSTANCE) == TIM6) || \
15638  ((INSTANCE) == TIM7) || \
15639  ((INSTANCE) == TIM8))
15640 
15641 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15642 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15643  ((INSTANCE) == TIM2) || \
15644  ((INSTANCE) == TIM3) || \
15645  ((INSTANCE) == TIM4) || \
15646  ((INSTANCE) == TIM5) || \
15647  ((INSTANCE) == TIM8) || \
15648  ((INSTANCE) == TIM9) || \
15649  ((INSTANCE) == TIM12))
15650 /********************** TIM Instances : 32 bit Counter ************************/
15651 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15652  ((INSTANCE) == TIM5))
15653 
15654 /***************** TIM Instances : external trigger input available ************/
15655 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15656  ((INSTANCE) == TIM2) || \
15657  ((INSTANCE) == TIM3) || \
15658  ((INSTANCE) == TIM4) || \
15659  ((INSTANCE) == TIM5) || \
15660  ((INSTANCE) == TIM8))
15661 
15662 /****************** TIM Instances : remapping capability **********************/
15663 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15664  ((INSTANCE) == TIM5) || \
15665  ((INSTANCE) == TIM11))
15666 
15667 /******************* TIM Instances : output(s) available **********************/
15668 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15669  ((((INSTANCE) == TIM1) && \
15670  (((CHANNEL) == TIM_CHANNEL_1) || \
15671  ((CHANNEL) == TIM_CHANNEL_2) || \
15672  ((CHANNEL) == TIM_CHANNEL_3) || \
15673  ((CHANNEL) == TIM_CHANNEL_4))) \
15674  || \
15675  (((INSTANCE) == TIM2) && \
15676  (((CHANNEL) == TIM_CHANNEL_1) || \
15677  ((CHANNEL) == TIM_CHANNEL_2) || \
15678  ((CHANNEL) == TIM_CHANNEL_3) || \
15679  ((CHANNEL) == TIM_CHANNEL_4))) \
15680  || \
15681  (((INSTANCE) == TIM3) && \
15682  (((CHANNEL) == TIM_CHANNEL_1) || \
15683  ((CHANNEL) == TIM_CHANNEL_2) || \
15684  ((CHANNEL) == TIM_CHANNEL_3) || \
15685  ((CHANNEL) == TIM_CHANNEL_4))) \
15686  || \
15687  (((INSTANCE) == TIM4) && \
15688  (((CHANNEL) == TIM_CHANNEL_1) || \
15689  ((CHANNEL) == TIM_CHANNEL_2) || \
15690  ((CHANNEL) == TIM_CHANNEL_3) || \
15691  ((CHANNEL) == TIM_CHANNEL_4))) \
15692  || \
15693  (((INSTANCE) == TIM5) && \
15694  (((CHANNEL) == TIM_CHANNEL_1) || \
15695  ((CHANNEL) == TIM_CHANNEL_2) || \
15696  ((CHANNEL) == TIM_CHANNEL_3) || \
15697  ((CHANNEL) == TIM_CHANNEL_4))) \
15698  || \
15699  (((INSTANCE) == TIM8) && \
15700  (((CHANNEL) == TIM_CHANNEL_1) || \
15701  ((CHANNEL) == TIM_CHANNEL_2) || \
15702  ((CHANNEL) == TIM_CHANNEL_3) || \
15703  ((CHANNEL) == TIM_CHANNEL_4))) \
15704  || \
15705  (((INSTANCE) == TIM9) && \
15706  (((CHANNEL) == TIM_CHANNEL_1) || \
15707  ((CHANNEL) == TIM_CHANNEL_2))) \
15708  || \
15709  (((INSTANCE) == TIM10) && \
15710  (((CHANNEL) == TIM_CHANNEL_1))) \
15711  || \
15712  (((INSTANCE) == TIM11) && \
15713  (((CHANNEL) == TIM_CHANNEL_1))) \
15714  || \
15715  (((INSTANCE) == TIM12) && \
15716  (((CHANNEL) == TIM_CHANNEL_1) || \
15717  ((CHANNEL) == TIM_CHANNEL_2))) \
15718  || \
15719  (((INSTANCE) == TIM13) && \
15720  (((CHANNEL) == TIM_CHANNEL_1))) \
15721  || \
15722  (((INSTANCE) == TIM14) && \
15723  (((CHANNEL) == TIM_CHANNEL_1))))
15724 
15725 /************ TIM Instances : complementary output(s) available ***************/
15726 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15727  ((((INSTANCE) == TIM1) && \
15728  (((CHANNEL) == TIM_CHANNEL_1) || \
15729  ((CHANNEL) == TIM_CHANNEL_2) || \
15730  ((CHANNEL) == TIM_CHANNEL_3))) \
15731  || \
15732  (((INSTANCE) == TIM8) && \
15733  (((CHANNEL) == TIM_CHANNEL_1) || \
15734  ((CHANNEL) == TIM_CHANNEL_2) || \
15735  ((CHANNEL) == TIM_CHANNEL_3))))
15736 
15737 /****************** TIM Instances : supporting counting mode selection ********/
15738 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15739  ((INSTANCE) == TIM2) || \
15740  ((INSTANCE) == TIM3) || \
15741  ((INSTANCE) == TIM4) || \
15742  ((INSTANCE) == TIM5) || \
15743  ((INSTANCE) == TIM8))
15744 
15745 /****************** TIM Instances : supporting clock division *****************/
15746 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15747  ((INSTANCE) == TIM2) || \
15748  ((INSTANCE) == TIM3) || \
15749  ((INSTANCE) == TIM4) || \
15750  ((INSTANCE) == TIM5) || \
15751  ((INSTANCE) == TIM8) || \
15752  ((INSTANCE) == TIM9) || \
15753  ((INSTANCE) == TIM10)|| \
15754  ((INSTANCE) == TIM11)|| \
15755  ((INSTANCE) == TIM12)|| \
15756  ((INSTANCE) == TIM13)|| \
15757  ((INSTANCE) == TIM14))
15758 
15759 /****************** TIM Instances : supporting commutation event generation ***/
15760 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15761  ((INSTANCE) == TIM8))
15762 
15763 
15764 /****************** TIM Instances : supporting OCxREF clear *******************/
15765 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15766  ((INSTANCE) == TIM2) || \
15767  ((INSTANCE) == TIM3) || \
15768  ((INSTANCE) == TIM4) || \
15769  ((INSTANCE) == TIM5) || \
15770  ((INSTANCE) == TIM8))
15771 
15772 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15773 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15774  ((INSTANCE) == TIM2) || \
15775  ((INSTANCE) == TIM3) || \
15776  ((INSTANCE) == TIM4) || \
15777  ((INSTANCE) == TIM5) || \
15778  ((INSTANCE) == TIM8) || \
15779  ((INSTANCE) == TIM9) || \
15780  ((INSTANCE) == TIM12))
15781 
15782 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15783 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15784  ((INSTANCE) == TIM2) || \
15785  ((INSTANCE) == TIM3) || \
15786  ((INSTANCE) == TIM4) || \
15787  ((INSTANCE) == TIM5) || \
15788  ((INSTANCE) == TIM8))
15789 
15790 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15791 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15792  ((INSTANCE) == TIM2) || \
15793  ((INSTANCE) == TIM3) || \
15794  ((INSTANCE) == TIM4) || \
15795  ((INSTANCE) == TIM5) || \
15796  ((INSTANCE) == TIM8) || \
15797  ((INSTANCE) == TIM9) || \
15798  ((INSTANCE) == TIM12))
15799 
15800 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15801 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15802  ((INSTANCE) == TIM2) || \
15803  ((INSTANCE) == TIM3) || \
15804  ((INSTANCE) == TIM4) || \
15805  ((INSTANCE) == TIM5) || \
15806  ((INSTANCE) == TIM8) || \
15807  ((INSTANCE) == TIM9) || \
15808  ((INSTANCE) == TIM12))
15809 
15810 /****************** TIM Instances : supporting repetition counter *************/
15811 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15812  ((INSTANCE) == TIM8))
15813 
15814 /****************** TIM Instances : supporting encoder interface **************/
15815 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15816  ((INSTANCE) == TIM2) || \
15817  ((INSTANCE) == TIM3) || \
15818  ((INSTANCE) == TIM4) || \
15819  ((INSTANCE) == TIM5) || \
15820  ((INSTANCE) == TIM8) || \
15821  ((INSTANCE) == TIM9) || \
15822  ((INSTANCE) == TIM12))
15823 /****************** TIM Instances : supporting Hall sensor interface **********/
15824 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15825  ((INSTANCE) == TIM2) || \
15826  ((INSTANCE) == TIM3) || \
15827  ((INSTANCE) == TIM4) || \
15828  ((INSTANCE) == TIM5) || \
15829  ((INSTANCE) == TIM8))
15830 /****************** TIM Instances : supporting the break function *************/
15831 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15832  ((INSTANCE) == TIM8))
15833 
15834 /******************** USART Instances : Synchronous mode **********************/
15835 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15836  ((INSTANCE) == USART2) || \
15837  ((INSTANCE) == USART3) || \
15838  ((INSTANCE) == USART6))
15839 
15840 /******************** UART Instances : Half-Duplex mode **********************/
15841 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15842  ((INSTANCE) == USART2) || \
15843  ((INSTANCE) == USART3) || \
15844  ((INSTANCE) == UART4) || \
15845  ((INSTANCE) == UART5) || \
15846  ((INSTANCE) == USART6))
15847 
15848 /* Legacy defines */
15849 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15850 
15851 /****************** UART Instances : Hardware Flow control ********************/
15852 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15853  ((INSTANCE) == USART2) || \
15854  ((INSTANCE) == USART3) || \
15855  ((INSTANCE) == UART4) || \
15856  ((INSTANCE) == UART5) || \
15857  ((INSTANCE) == USART6))
15858 /******************** UART Instances : LIN mode **********************/
15859 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15860 
15861 /********************* UART Instances : Smart card mode ***********************/
15862 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15863  ((INSTANCE) == USART2) || \
15864  ((INSTANCE) == USART3) || \
15865  ((INSTANCE) == USART6))
15866 
15867 /*********************** UART Instances : IRDA mode ***************************/
15868 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15869  ((INSTANCE) == USART2) || \
15870  ((INSTANCE) == USART3) || \
15871  ((INSTANCE) == UART4) || \
15872  ((INSTANCE) == UART5) || \
15873  ((INSTANCE) == USART6))
15874 
15875 
15876 /*********************** PCD Instances ****************************************/
15877 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15878  ((INSTANCE) == USB_OTG_HS))
15879 
15880 /*********************** HCD Instances ****************************************/
15881 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15882  ((INSTANCE) == USB_OTG_HS))
15883 
15884 /****************************** SDIO Instances ********************************/
15885 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15886 
15887 /****************************** IWDG Instances ********************************/
15888 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15889 
15890 /****************************** WWDG Instances ********************************/
15891 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15892 
15893 
15894 /****************************** QSPI Instances ********************************/
15895 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15896 
15897 /******************************* CEC Instances ********************************/
15898 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
15899 
15900 /***************************** FMPI2C Instances *******************************/
15901 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15902 #define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
15903 
15904 /******************************* SPDIFRX Instances ********************************/
15905 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
15906 /****************************** USB Exported Constants ************************/
15907 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
15908 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15909 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15910 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15911 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
15912 #define USB_OTG_HS_MAX_IN_ENDPOINTS 9U /* Including EP0 */
15913 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 9U /* Including EP0 */
15914 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
15915 
15916 /*
15917  * @brief Specific devices reset values definitions
15918  */
15919 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
15920 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
15921 #define RCC_PLLSAICFGR_RST_VALUE 0x04003010U
15922 
15923 #define RCC_MAX_FREQUENCY 180000000U
15924 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
15925 #define RCC_MAX_FREQUENCY_SCALE2 168000000U
15926 #define RCC_MAX_FREQUENCY_SCALE3 120000000U
15927 #define RCC_PLLVCO_OUTPUT_MIN 100000000U
15928 #define RCC_PLLVCO_INPUT_MIN 950000U
15929 #define RCC_PLLVCO_INPUT_MAX 2100000U
15930 #define RCC_PLLVCO_OUTPUT_MAX 432000000U
15932 #define RCC_PLLN_MIN_VALUE 50U
15933 #define RCC_PLLN_MAX_VALUE 432U
15934 
15935 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U
15936 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U
15937 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U
15938 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U
15939 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U
15941 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U
15942 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U
15943 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U
15944 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U
15945 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U
15947 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U
15948 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U
15949 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U
15951 /******************************************************************************/
15952 /* For a painless codes migration between the STM32F4xx device product */
15953 /* lines, the aliases defined below are put in place to overcome the */
15954 /* differences in the interrupt handlers and IRQn definitions. */
15955 /* No need to update developed interrupt code when moving across */
15956 /* product lines within the same STM32F4 Family */
15957 /******************************************************************************/
15958 /* Aliases for __IRQn */
15959 #define FSMC_IRQn FMC_IRQn
15960 
15961 /* Aliases for __IRQHandler */
15962 #define FSMC_IRQHandler FMC_IRQHandler
15963 #define QuadSPI_IRQHandler QUADSPI_IRQHandler
15964 
15977 #ifdef __cplusplus
15978 }
15979 #endif /* __cplusplus */
15980 
15981 #endif /* __STM32F446xx_H */
__IO
#define __IO
Definition: core_armv8mbl.h:196
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f446xx.h:66
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f446xx.h:74
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32f446xx.h:85
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32f446xx.h:90
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32f446xx.h:99
SDIO_IRQn
@ SDIO_IRQn
Definition: stm32f446xx.h:126
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32f446xx.h:80
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32f446xx.h:160
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32f446xx.h:150
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32f446xx.h:133
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32f446xx.h:144
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f446xx.h:109
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f446xx.h:110
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f446xx.h:69
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32f446xx.h:156
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f446xx.h:107
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f446xx.h:105
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32f446xx.h:145
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32f446xx.h:120
USART2_IRQn
@ USART2_IRQn
Definition: stm32f446xx.h:115
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32f446xx.h:136
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f446xx.h:72
ADC_IRQn
@ ADC_IRQn
Definition: stm32f446xx.h:95
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32f446xx.h:128
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f446xx.h:113
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32f446xx.h:132
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition: stm32f446xx.h:141
RCC_IRQn
@ RCC_IRQn
Definition: stm32f446xx.h:82
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32f446xx.h:131
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32f446xx.h:149
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f446xx.h:111
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32f446xx.h:158
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32f446xx.h:123
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f446xx.h:71
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f446xx.h:75
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32f446xx.h:148
FMPI2C1_ER_IRQn
@ FMPI2C1_ER_IRQn
Definition: stm32f446xx.h:162
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32f446xx.h:147
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition: stm32f446xx.h:139
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f446xx.h:70
CEC_IRQn
@ CEC_IRQn
Definition: stm32f446xx.h:159
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f446xx.h:73
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f446xx.h:81
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32f446xx.h:143
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f446xx.h:77
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f446xx.h:108
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f446xx.h:106
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32f446xx.h:134
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition: stm32f446xx.h:96
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32f446xx.h:151
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32f446xx.h:88
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f446xx.h:117
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32f446xx.h:155
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition: stm32f446xx.h:102
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f446xx.h:100
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32f446xx.h:89
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32f446xx.h:142
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32f446xx.h:119
FPU_IRQn
@ FPU_IRQn
Definition: stm32f446xx.h:154
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32f446xx.h:121
USART6_IRQn
@ USART6_IRQn
Definition: stm32f446xx.h:146
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f446xx.h:112
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32f446xx.h:152
PVD_IRQn
@ PVD_IRQn
Definition: stm32f446xx.h:78
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f446xx.h:103
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition: stm32f446xx.h:101
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition: stm32f446xx.h:140
FMC_IRQn
@ FMC_IRQn
Definition: stm32f446xx.h:125
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f446xx.h:83
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition: stm32f446xx.h:97
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f446xx.h:87
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32f446xx.h:157
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32f446xx.h:135
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32f446xx.h:79
UART5_IRQn
@ UART5_IRQn
Definition: stm32f446xx.h:130
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32f446xx.h:93
DCMI_IRQn
@ DCMI_IRQn
Definition: stm32f446xx.h:153
USART1_IRQn
@ USART1_IRQn
Definition: stm32f446xx.h:114
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f446xx.h:86
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f446xx.h:68
UART4_IRQn
@ UART4_IRQn
Definition: stm32f446xx.h:129
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f446xx.h:122
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f446xx.h:84
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32f446xx.h:137
FMPI2C1_EV_IRQn
@ FMPI2C1_EV_IRQn
Definition: stm32f446xx.h:161
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32f446xx.h:127
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32f446xx.h:124
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32f446xx.h:92
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32f446xx.h:94
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f446xx.h:104
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition: stm32f446xx.h:138
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32f446xx.h:98
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32f446xx.h:91
USART3_IRQn
@ USART3_IRQn
Definition: stm32f446xx.h:116
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f446xx.h:118
ADC_Common_TypeDef
Definition: stm32f446xx.h:206
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32f446xx.h:209
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f446xx.h:207
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f446xx.h:208
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f446xx.h:182
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f446xx.h:194
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:185
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f446xx.h:192
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f446xx.h:200
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f446xx.h:196
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f446xx.h:197
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f446xx.h:195
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f446xx.h:186
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:202
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f446xx.h:199
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:184
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f446xx.h:191
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:183
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f446xx.h:187
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f446xx.h:188
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f446xx.h:189
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f446xx.h:198
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f446xx.h:201
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f446xx.h:190
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f446xx.h:193
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f446xx.h:231
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f446xx.h:232
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f446xx.h:233
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f446xx.h:235
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f446xx.h:234
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f446xx.h:243
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f446xx.h:245
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f446xx.h:244
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f446xx.h:219
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f446xx.h:220
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f446xx.h:221
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f446xx.h:222
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f446xx.h:223
CAN_TypeDef
Controller Area Network.
Definition: stm32f446xx.h:253
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f446xx.h:254
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f446xx.h:266
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f446xx.h:272
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f446xx.h:259
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f446xx.h:258
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f446xx.h:260
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f446xx.h:268
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f446xx.h:273
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f446xx.h:269
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f446xx.h:256
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f446xx.h:261
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f446xx.h:257
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f446xx.h:271
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f446xx.h:267
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f446xx.h:270
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f446xx.h:255
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32f446xx.h:284
CEC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f446xx.h:286
CEC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:285
CEC_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f446xx.h:287
CEC_TypeDef::IER
__IO uint32_t IER
Definition: stm32f446xx.h:290
CEC_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f446xx.h:288
CEC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f446xx.h:289
CRC_TypeDef
CRC calculation unit.
Definition: stm32f446xx.h:297
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:298
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f446xx.h:300
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f446xx.h:301
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f446xx.h:299
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:302
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f446xx.h:310
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f446xx.h:321
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f446xx.h:323
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:324
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:311
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f446xx.h:315
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f446xx.h:318
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f446xx.h:312
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f446xx.h:322
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f446xx.h:314
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f446xx.h:317
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f446xx.h:316
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f446xx.h:320
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f446xx.h:313
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f446xx.h:319
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f446xx.h:332
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f446xx.h:336
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f446xx.h:333
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:334
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f446xx.h:335
DCMI_TypeDef
DCMI.
Definition: stm32f446xx.h:344
DCMI_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f446xx.h:350
DCMI_TypeDef::CWSIZER
__IO uint32_t CWSIZER
Definition: stm32f446xx.h:354
DCMI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:346
DCMI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:355
DCMI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:345
DCMI_TypeDef::CWSTRTR
__IO uint32_t CWSTRTR
Definition: stm32f446xx.h:353
DCMI_TypeDef::ESCR
__IO uint32_t ESCR
Definition: stm32f446xx.h:351
DCMI_TypeDef::IER
__IO uint32_t IER
Definition: stm32f446xx.h:348
DCMI_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32f446xx.h:349
DCMI_TypeDef::RISR
__IO uint32_t RISR
Definition: stm32f446xx.h:347
DCMI_TypeDef::ESUR
__IO uint32_t ESUR
Definition: stm32f446xx.h:352
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f446xx.h:363
DMA_Stream_TypeDef::M1AR
__IO uint32_t M1AR
Definition: stm32f446xx.h:368
DMA_Stream_TypeDef::NDTR
__IO uint32_t NDTR
Definition: stm32f446xx.h:365
DMA_Stream_TypeDef::M0AR
__IO uint32_t M0AR
Definition: stm32f446xx.h:367
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f446xx.h:369
DMA_Stream_TypeDef::PAR
__IO uint32_t PAR
Definition: stm32f446xx.h:366
DMA_Stream_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:364
DMA_TypeDef
Definition: stm32f446xx.h:373
DMA_TypeDef::HISR
__IO uint32_t HISR
Definition: stm32f446xx.h:375
DMA_TypeDef::LIFCR
__IO uint32_t LIFCR
Definition: stm32f446xx.h:376
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
Definition: stm32f446xx.h:377
DMA_TypeDef::LISR
__IO uint32_t LISR
Definition: stm32f446xx.h:374
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f446xx.h:385
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f446xx.h:391
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f446xx.h:386
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f446xx.h:390
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f446xx.h:387
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f446xx.h:388
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f446xx.h:389
FLASH_TypeDef
FLASH Registers.
Definition: stm32f446xx.h:399
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition: stm32f446xx.h:406
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:403
FLASH_TypeDef::OPTCR
__IO uint32_t OPTCR
Definition: stm32f446xx.h:405
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:404
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f446xx.h:402
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f446xx.h:401
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f446xx.h:400
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f446xx.h:423
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f446xx.h:414
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f446xx.h:432
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:434
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32f446xx.h:436
FMC_Bank3_TypeDef::RESERVED
uint32_t RESERVED
Definition: stm32f446xx.h:437
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32f446xx.h:438
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32f446xx.h:433
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32f446xx.h:435
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f446xx.h:446
FMC_Bank5_6_TypeDef::SDSR
__IO uint32_t SDSR
Definition: stm32f446xx.h:451
FMC_Bank5_6_TypeDef::SDRTR
__IO uint32_t SDRTR
Definition: stm32f446xx.h:450
FMC_Bank5_6_TypeDef::SDCMR
__IO uint32_t SDCMR
Definition: stm32f446xx.h:449
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f446xx.h:509
FMPI2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32f446xx.h:515
FMPI2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f446xx.h:516
FMPI2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32f446xx.h:518
FMPI2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f446xx.h:519
FMPI2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32f446xx.h:514
FMPI2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:510
FMPI2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f446xx.h:520
FMPI2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:511
FMPI2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f446xx.h:517
FMPI2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f446xx.h:512
FMPI2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f446xx.h:513
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f446xx.h:459
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f446xx.h:462
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f446xx.h:463
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f446xx.h:465
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f446xx.h:461
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f446xx.h:467
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f446xx.h:460
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f446xx.h:466
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f446xx.h:464
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f446xx.h:491
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:493
I2C_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f446xx.h:499
I2C_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:496
I2C_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32f446xx.h:497
I2C_TypeDef::FLTR
__IO uint32_t FLTR
Definition: stm32f446xx.h:501
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f446xx.h:495
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:492
I2C_TypeDef::TRISE
__IO uint32_t TRISE
Definition: stm32f446xx.h:500
I2C_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f446xx.h:498
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f446xx.h:494
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f446xx.h:528
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f446xx.h:530
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f446xx.h:529
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:532
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f446xx.h:531
PWR_TypeDef
Power Control.
Definition: stm32f446xx.h:541
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f446xx.h:543
PWR_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:542
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f446xx.h:707
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32f446xx.h:718
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32f446xx.h:712
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32f446xx.h:719
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32f446xx.h:717
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f446xx.h:709
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f446xx.h:713
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32f446xx.h:720
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32f446xx.h:714
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:710
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f446xx.h:711
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:708
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:716
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32f446xx.h:715
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f446xx.h:551
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f446xx.h:577
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f446xx.h:554
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f446xx.h:573
RCC_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32f446xx.h:571
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32f446xx.h:553
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32f446xx.h:557
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32f446xx.h:558
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f446xx.h:561
RCC_TypeDef::SSCGR
__IO uint32_t SSCGR
Definition: stm32f446xx.h:580
RCC_TypeDef::APB1LPENR
__IO uint32_t APB1LPENR
Definition: stm32f446xx.h:574
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f446xx.h:560
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f446xx.h:568
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f446xx.h:559
RCC_TypeDef::CKGATENR
__IO uint32_t CKGATENR
Definition: stm32f446xx.h:584
RCC_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32f446xx.h:575
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f446xx.h:578
RCC_TypeDef::DCKCFGR
__IO uint32_t DCKCFGR
Definition: stm32f446xx.h:583
RCC_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32f446xx.h:570
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f446xx.h:566
RCC_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32f446xx.h:572
RCC_TypeDef::DCKCFGR2
__IO uint32_t DCKCFGR2
Definition: stm32f446xx.h:585
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:552
RCC_TypeDef::PLLI2SCFGR
__IO uint32_t PLLI2SCFGR
Definition: stm32f446xx.h:581
RCC_TypeDef::PLLSAICFGR
__IO uint32_t PLLSAICFGR
Definition: stm32f446xx.h:582
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32f446xx.h:565
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32f446xx.h:556
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f446xx.h:555
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f446xx.h:567
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32f446xx.h:564
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32f446xx.h:563
RTC_TypeDef
Real-Time Clock.
Definition: stm32f446xx.h:593
RTC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32f446xx.h:613
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f446xx.h:622
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f446xx.h:619
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f446xx.h:627
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32f446xx.h:632
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32f446xx.h:630
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f446xx.h:606
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f446xx.h:608
RTC_TypeDef::CALIBR
__IO uint32_t CALIBR
Definition: stm32f446xx.h:600
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f446xx.h:612
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f446xx.h:594
RTC_TypeDef::TAFCR
__IO uint32_t TAFCR
Definition: stm32f446xx.h:610
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f446xx.h:615
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f446xx.h:597
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f446xx.h:598
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f446xx.h:624
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f446xx.h:605
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f446xx.h:618
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f446xx.h:626
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:596
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f446xx.h:620
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f446xx.h:629
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:595
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f446xx.h:625
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32f446xx.h:631
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f446xx.h:602
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f446xx.h:621
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32f446xx.h:633
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f446xx.h:607
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f446xx.h:616
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f446xx.h:614
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f446xx.h:623
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f446xx.h:617
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f446xx.h:611
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f446xx.h:603
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f446xx.h:601
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f446xx.h:599
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f446xx.h:628
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f446xx.h:609
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f446xx.h:604
SAI_Block_TypeDef
Definition: stm32f446xx.h:646
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32f446xx.h:653
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32f446xx.h:649
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:647
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:654
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32f446xx.h:650
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:652
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:648
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f446xx.h:651
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f446xx.h:641
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f446xx.h:642
SDIO_TypeDef
SD host Interface.
Definition: stm32f446xx.h:662
SDIO_TypeDef::RESP4
__IO const uint32_t RESP4
Definition: stm32f446xx.h:671
SDIO_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32f446xx.h:665
SDIO_TypeDef::FIFOCNT
__IO const uint32_t FIFOCNT
Definition: stm32f446xx.h:680
SDIO_TypeDef::STA
__IO const uint32_t STA
Definition: stm32f446xx.h:676
SDIO_TypeDef::RESP3
__IO const uint32_t RESP3
Definition: stm32f446xx.h:670
SDIO_TypeDef::RESP1
__IO const uint32_t RESP1
Definition: stm32f446xx.h:668
SDIO_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32f446xx.h:672
SDIO_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32f446xx.h:663
SDIO_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32f446xx.h:674
SDIO_TypeDef::DCOUNT
__IO const uint32_t DCOUNT
Definition: stm32f446xx.h:675
SDIO_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32f446xx.h:678
SDIO_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32f446xx.h:673
SDIO_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32f446xx.h:682
SDIO_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32f446xx.h:666
SDIO_TypeDef::RESPCMD
__IO const uint32_t RESPCMD
Definition: stm32f446xx.h:667
SDIO_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f446xx.h:677
SDIO_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32f446xx.h:664
SDIO_TypeDef::RESP2
__IO const uint32_t RESP2
Definition: stm32f446xx.h:669
SPDIFRX_TypeDef
SPDIFRX Interface.
Definition: stm32f446xx.h:728
SPDIFRX_TypeDef::IMR
__IO uint16_t IMR
Definition: stm32f446xx.h:730
SPDIFRX_TypeDef::RESERVED2
uint16_t RESERVED2
Definition: stm32f446xx.h:738
SPDIFRX_TypeDef::DIR
__IO uint32_t DIR
Definition: stm32f446xx.h:737
SPDIFRX_TypeDef::IFCR
__IO uint16_t IFCR
Definition: stm32f446xx.h:733
SPDIFRX_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f446xx.h:736
SPDIFRX_TypeDef::RESERVED0
uint16_t RESERVED0
Definition: stm32f446xx.h:731
SPDIFRX_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:735
SPDIFRX_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:732
SPDIFRX_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f446xx.h:734
SPDIFRX_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:729
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f446xx.h:690
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:694
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f446xx.h:697
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:693
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:692
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f446xx.h:698
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f446xx.h:695
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f446xx.h:696
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:691
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f446xx.h:699
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f446xx.h:476
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32f446xx.h:477
SYSCFG_TypeDef::PMC
__IO uint32_t PMC
Definition: stm32f446xx.h:478
SYSCFG_TypeDef::CMPCR
__IO uint32_t CMPCR
Definition: stm32f446xx.h:481
SYSCFG_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f446xx.h:483
TIM_TypeDef
TIM.
Definition: stm32f446xx.h:746
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f446xx.h:752
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f446xx.h:760
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f446xx.h:753
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f446xx.h:764
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f446xx.h:750
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f446xx.h:761
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f446xx.h:763
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f446xx.h:749
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f446xx.h:758
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:748
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f446xx.h:756
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f446xx.h:765
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:747
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f446xx.h:754
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f446xx.h:762
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f446xx.h:767
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:751
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f446xx.h:757
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f446xx.h:759
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f446xx.h:755
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f446xx.h:766
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f446xx.h:775
USART_TypeDef::DR
__IO uint32_t DR
Definition: stm32f446xx.h:777
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f446xx.h:779
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f446xx.h:778
USART_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:776
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f446xx.h:780
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f446xx.h:782
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f446xx.h:781
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f446xx.h:830
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32f446xx.h:841
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32f446xx.h:832
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32f446xx.h:833
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32f446xx.h:838
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32f446xx.h:839
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32f446xx.h:847
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32f446xx.h:837
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32f446xx.h:844
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32f446xx.h:848
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition: stm32f446xx.h:840
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32f446xx.h:842
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32f446xx.h:845
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f446xx.h:834
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32f446xx.h:835
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32f446xx.h:831
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32f446xx.h:850
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32f446xx.h:846
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32f446xx.h:836
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32f446xx.h:843
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f446xx.h:799
USB_OTG_GlobalTypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: stm32f446xx.h:820
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32f446xx.h:808
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32f446xx.h:801
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32f446xx.h:805
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32f446xx.h:803
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32f446xx.h:802
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32f446xx.h:806
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32f446xx.h:800
USB_OTG_GlobalTypeDef::Reserved6
uint32_t Reserved6
Definition: stm32f446xx.h:817
USB_OTG_GlobalTypeDef::GHWCFG3
__IO uint32_t GHWCFG3
Definition: stm32f446xx.h:816
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32f446xx.h:814
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32f446xx.h:804
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32f446xx.h:807
USB_OTG_GlobalTypeDef::Reserved
uint32_t Reserved
Definition: stm32f446xx.h:819
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32f446xx.h:811
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32f446xx.h:813
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32f446xx.h:810
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32f446xx.h:822
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32f446xx.h:809
USB_OTG_GlobalTypeDef::GLPMCFG
__IO uint32_t GLPMCFG
Definition: stm32f446xx.h:818
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f446xx.h:900
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32f446xx.h:905
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32f446xx.h:902
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32f446xx.h:906
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32f446xx.h:903
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32f446xx.h:901
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32f446xx.h:904
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f446xx.h:886
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32f446xx.h:890
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32f446xx.h:888
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32f446xx.h:893
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32f446xx.h:887
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32f446xx.h:889
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32f446xx.h:891
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32f446xx.h:892
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f446xx.h:857
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32f446xx.h:864
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f446xx.h:861
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32f446xx.h:865
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32f446xx.h:858
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32f446xx.h:863
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f446xx.h:859
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32f446xx.h:862
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32f446xx.h:860
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f446xx.h:872
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32f446xx.h:875
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32f446xx.h:878
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f446xx.h:876
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32f446xx.h:877
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f446xx.h:874
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32f446xx.h:873
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f446xx.h:790
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f446xx.h:793
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f446xx.h:791
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f446xx.h:792
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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